boards: pcbcupid : Add glyph c6 board

boards/pcbcupid/glyph_c6/Kconfig

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+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+	int
+	default 4096 if BOARD_GLYPH_C6_ESP32C6_HPCORE
+	default 256 if BOARD_GLYPH_C6_ESP32C6_LPCORE

boards/pcbcupid/glyph_c6/Kconfig.glyph_c6

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+# glyph c6 board configuration
+
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# Copyright (c) 2025 Muhammed Asif
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_GLYPH_C6
+	select SOC_ESP32_C6_WROOM_1U_N4
+	select SOC_ESP32C6_HPCORE if BOARD_GLYPH_C6_ESP32C6_HPCORE
+	select SOC_ESP32C6_LPCORE if BOARD_GLYPH_C6_ESP32C6_LPCORE

boards/pcbcupid/glyph_c6/Kconfig.sysbuild

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+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+choice BOOTLOADER
+	default BOOTLOADER_MCUBOOT
+endchoice
+
+choice BOOT_SIGNATURE_TYPE
+	default BOOT_SIGNATURE_TYPE_NONE
+endchoice

boards/pcbcupid/glyph_c6/board.cmake

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+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
+  set(OPENOCD OPENOCD-NOTFOUND)
+endif()
+find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
+
+include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/pcbcupid/glyph_c6/board.yml

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+board:
+  name: glyph_c6
+  full_name: Glyph-C6
+  vendor: pcbcupid
+  socs:
+  - name: esp32c6

boards/pcbcupid/glyph_c6/doc/index.rst

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+.. zephyr:board:: glyph_c6
+
+Overview
+********
+
+Glyph-C6 is powered by ESP32-C6 SoC.
+It consists of a high-performance (HP) 32-bit RISC-V processor, which can be clocked up to 160 MHz,
+and a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz.
+It has a 512KB SRAM, and works with 4MB external SPI flash.
+For more information, check `Glyph-C6`_.
+
+Hardware
+********
+
+ESP32-C6 is Espressif's first Wi-Fi 6 SoC integrating 2.4 GHz Wi-Fi 6, Bluetooth 5.3 (LE) and the
+802.15.4 protocol. ESP32-C6 achieves an industry-leading RF performance, with reliable security
+features and multiple memory resources for IoT products.
+It consists of a high-performance (HP) 32-bit RISC-V processor, which can be clocked up to 160 MHz,
+and a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz.
+It has a 320KB ROM, a 512KB SRAM, and works with external flash.
+
+Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing.
+Developers can either connect peripherals with jumper wires or mount glyph c6 on
+a breadboard.
+
+ESP32-C6 includes the following features:
+
+- 32-bit core RISC-V microcontroller with a clock speed of up to 160 MHz
+- 400 KB of internal RAM
+- WiFi 802.11 ax 2.4GHz
+- Fully compatible with IEEE 802.11b/g/n protocol
+- Bluetooth LE: Bluetooth 5.3 certified
+- Internal co-existence mechanism between Wi-Fi and Bluetooth to share the same antenna
+- IEEE 802.15.4 (Zigbee and Thread)
+
+Digital interfaces:
+
+- 30x GPIOs (QFN40), or 22x GPIOs (QFN32)
+- 2x UART
+- 1x Low-power (LP) UART
+- 1x General purpose SPI
+- 1x I2C
+- 1x Low-power (LP) I2C
+- 1x I2S
+- 1x Pulse counter
+- 1x USB Serial/JTAG controller
+- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0)
+- 1x SDIO 2.0 slave controller
+- LED PWM controller, up to 6 channels
+- 1x Motor control PWM (MCPWM)
+- 1x Remote control peripehral
+- 1x Parallel IO interface (PARLIO)
+- General DMA controller (GDMA), with 3 transmit channels and 3 receive channels
+- Event task matrix (ETM)
+
+Analog interfaces:
+
+- 1x 12-bit SAR ADCs, up to 7 channels
+- 1x temperature sensor
+
+Timers:
+
+- 1x 52-bit system timer
+- 1x 54-bit general-purpose timers
+- 3x Watchdog timers
+- 1x Analog watchdog timer
+
+Low Power:
+
+- Four power modes designed for typical scenarios: Active, Modem-sleep, Light-sleep, Deep-sleep
+
+Security:
+
+- Secure boot
+- Flash encryption
+- 4-Kbit OTP, up to 1792 bits for users
+- Cryptographic hardware acceleration: (AES-128/256, ECC, HMAC, RSA, SHA, Digital signature, Hash)
+- Random number generator (RNG)
+
+Memory and Storage:
+
+- While the Glyph ESP32-C6 has 512KB onboard SRAM, it also relies on an external flash chip for program storage.
+  On this board, there is 4 MB of flash memory, which is shared between the code, file storage and OTA
+
+For more information, check the datasheet at `ESP32-C6 Datasheet`_ or the technical reference
+manual at `ESP32-C6 Technical Reference Manual`_.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+System Requirements
+*******************
+
+Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
+below to retrieve those files.
+
+.. code-block:: console
+
+   west blobs fetch hal_espressif
+
+.. note::
+
+   It is recommended running the command above after :file:`west update`.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+.. include:: ../../../espressif/common/building-flashing.rst
+   :start-after: espressif-building-flashing
+
+.. include:: ../../../espressif/common/board-variants.rst
+   :start-after: espressif-board-variants
+
+Debugging
+=========
+
+.. include:: ../../../espressif/common/openocd-debugging.rst
+   :start-after: espressif-openocd-debugging
+
+Low-Power CPU (LP CORE)
+***********************
+
+The ESP32-C6 SoC has two RISC-V cores: the High-Performance Core (HP CORE) and the Low-Power Core (LP CORE).
+The LP Core features ultra low power consumption, an interrupt controller, a debug module and a system bus
+interface for memory and peripheral access.
+
+The LP Core is in sleep mode by default. It has two application scenarios:
+
+- Power insensitive scenario: When the High-Performance CPU (HP Core) is active, the LP Core can assist the HP CPU with some speed and efficiency-insensitive controls and computations.
+- Power sensitive scenario: When the HP CPU is in the power-down state to save power, the LP Core can be woken up to handle some external wake-up events.
+
+For more information, check the datasheet at `ESP32-C6 Datasheet`_ or the technical reference
+manual at `ESP32-C6 Technical Reference Manual`_.
+
+The LP Core support is fully integrated with :ref:`sysbuild`. The user can enable the LP Core by adding
+the following configuration to the project:
+
+.. code:: cfg
+
+   CONFIG_ULP_COPROC_ENABLED=y
+
+See :zephyr:code-sample-category:`lp-core` folder as code reference.
+
+References
+**********
+
+.. target-notes::
+
+.. _`Glyph-C6`: https://learn.pcbcupid.com/boards/glyph-c6/overview
+.. _`ESP32-C6 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf
+.. _`ESP32-C6 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c6_technical_reference_manual_en.pdf
+.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases

boards/pcbcupid/glyph_c6/glyph_c6-pinctrl.dtsi

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+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2025 Muhammed Asif
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+#include <dt-bindings/pinctrl/esp32c6-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/esp32c6-gpio-sigmap.h>
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0_TX_GPIO16>;
+			output-high;
+		};
+
+		group2 {
+			pinmux = <UART0_RX_GPIO17>;
+			bias-pull-up;
+		};
+	};
+};

boards/pcbcupid/glyph_c6/glyph_c6_hpcore.dts

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+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2025 Muhammed Asif
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <espressif/esp32c6/esp32c6_wroom_n4.dtsi>
+#include "glyph_c6-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <espressif/partitions_0x0_default.dtsi>
+
+/ {
+	model = "PCB Cupid Glyph ESP32C6 HPCORE";
+	compatible = "pcbcupid,glyph-c6";
+
+	chosen {
+		zephyr,sram = &sramhp;
+		zephyr,console = &usb_serial;
+		zephyr,shell-uart = &usb_serial;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+	};
+
+	aliases {
+		led0 = &red_led;
+		sw0 = &button0;
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		red_led: led_0 {
+			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+			label = "User LED0";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		button0: button_0 {
+			gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Boot";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+};
+
+&usb_serial {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};

boards/pcbcupid/glyph_c6/glyph_c6_hpcore.yaml

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+identifier: glyph_c6/esp32c6/hpcore
+name: Glyph ESP32C6 HP Core
+vendor: pcbcupid
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - uart

boards/pcbcupid/glyph_c6/glyph_c6_hpcore_defconfig

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+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y

boards/pcbcupid/glyph_c6/glyph_c6_lpcore.dts

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+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2025 Muhammed Asif
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <espressif/esp32c6/esp32c6_lpcore_wroom_n4.dtsi>
+#include <espressif/partitions_0x0_default.dtsi>
+
+/ {
+	model = "PCB Cupid Glyph ESP32C6 LPCORE";
+	compatible = "pcbcupid,glyph-c6";
+
+	chosen {
+		zephyr,sram = &sramlp;
+		zephyr,code-partition = &slot0_lpcore_partition;
+	};
+};

boards/pcbcupid/glyph_c6/glyph_c6_lpcore.yaml

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+identifier: glyph_c6/esp32c6/lpcore
+name: Glyph ESP32C6 LP Core
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+supported:
+  - cpu
+testing:
+  only_tags:
+    - introduction
+  ignore_tags:
+    - kernel
+    - posix
+    - chre
+    - cpp
+vendor: pcbcupid

boards/pcbcupid/glyph_c6/glyph_c6_lpcore_defconfig

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+# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+# Memory protection
+CONFIG_THREAD_STACK_INFO=n
+CONFIG_THREAD_CUSTOM_DATA=n
+
+# Boot
+CONFIG_BOOT_BANNER=n
+
+# Console
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_PRINTK=n
+CONFIG_CBPRINTF_NANO=y
+
+# Build
+CONFIG_SIZE_OPTIMIZATIONS=y
+CONFIG_BUSYWAIT_CPU_LOOPS_PER_USEC=4

boards/pcbcupid/glyph_c6/support/openocd.cfg

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+# ESP32C6 has built-in JTAG interface over USB port in pins GPIO13/GPIO12 (D-/D+).
+set ESP_RTOS none
+
+source [find board/esp32c6-builtin.cfg]

boards/pcbcupid/index.rst

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+.. _boards-pcbcupid:
+
+PCB Cupid
+#########
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*

dts/bindings/vendor-prefixes.txt

@@ -1,4 +1,4 @@
 # Device tree binding vendor prefix registry. Keep this list in
 # alphabetical order.
 #
 # This isn't an exhaustive list, but you should add new prefixes to it
@@ -516,6 +516,7 @@
 parade	Parade Technologies Inc.
 parallax	Parallax Inc.
 particle	Particle.io
+pcbcupid	PCB Cupid
 pda	Precision Design Associates, Inc.
 peacefair	Ningbo Peacefair Electronic Technology Co., Ltd
 peregrine	Peregrine Consultoria e Servicos