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drivers: memc: stm32: HAL return value handling #97282

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drivers: memc: stm32: HAL return value handling #97282

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43660c7
drivers: memc: test STM32 HAL return value in OSPI PSRAM driver
etienne-lms Oct 9, 2025
eadf284
drivers: memc: test STM32 HAL return value in SDRAM driver
etienne-lms Oct 9, 2025
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6 changes: 4 additions & 2 deletions drivers/memc/memc_stm32_ospi_psram.c
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Original file line number Diff line number Diff line change
Expand Up @@ -372,8 +372,10 @@ static int memc_stm32_ospi_psram_init(const struct device *dev)
ll_dlyb_cfg.PhaseSel /= 4;
ll_dlyb_cfg_test = ll_dlyb_cfg;

HAL_OSPI_DLYB_SetConfig(hospi, &ll_dlyb_cfg);
HAL_OSPI_DLYB_GetConfig(hospi, &ll_dlyb_cfg);
if ((HAL_OSPI_DLYB_SetConfig(hospi, &ll_dlyb_cfg) != HAL_OK) ||
(HAL_OSPI_DLYB_GetConfig(hospi, &ll_dlyb_cfg) != HAL_OK)) {
return -EIO;
}

if ((ll_dlyb_cfg.PhaseSel != ll_dlyb_cfg_test.PhaseSel) ||
(ll_dlyb_cfg.Units != ll_dlyb_cfg_test.Units)) {
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27 changes: 19 additions & 8 deletions drivers/memc/memc_stm32_sdram.c
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Original file line number Diff line number Diff line change
Expand Up @@ -46,9 +46,10 @@ static int memc_stm32_sdram_init(const struct device *dev)
sdram.State = HAL_SDRAM_STATE_RESET;
memcpy(&sdram.Init, &config->banks[i].init, sizeof(sdram.Init));

(void)HAL_SDRAM_Init(
&sdram,
(FMC_SDRAM_TimingTypeDef *)&config->banks[i].timing);
if (HAL_SDRAM_Init(&sdram,
(FMC_SDRAM_TimingTypeDef *)&config->banks[i].timing) != HAL_OK) {
return -EIO;
}
}

/* SDRAM initialization sequence */
Expand All @@ -65,24 +66,34 @@ static int memc_stm32_sdram_init(const struct device *dev)

/* enable clock */
sdram_cmd.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
(void)HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U);
if (HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U) != HAL_OK) {
return -EIO;
}

k_usleep(config->power_up_delay);

/* pre-charge all */
sdram_cmd.CommandMode = FMC_SDRAM_CMD_PALL;
(void)HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U);
if (HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U) != HAL_OK) {
return -EIO;
}

/* auto-refresh */
sdram_cmd.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
(void)HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U);
if (HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U) != HAL_OK) {
return -EIO;
}

/* load mode */
sdram_cmd.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
(void)HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U);
if (HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U) != HAL_OK) {
return -EIO;
}

/* program refresh count */
(void)HAL_SDRAM_ProgramRefreshRate(&sdram, config->refresh_rate);
if (HAL_SDRAM_ProgramRefreshRate(&sdram, config->refresh_rate) != HAL_OK) {
return -EIO;
}

return 0;
}
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