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dts: stm32h7rs: Add SDMMC support for STM32H7RS series #97293

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dts: stm32h7rs: Add SDMMC support for STM32H7RS series #97293

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cf59a9e
dts: stm32: stm32h7rs: Add sdmmc1 and sdmmc2 configuration
bricle Aug 25, 2025
ab5dce7
boards: art_pi2: Add SDMMC1 configuration with PLL2 kernel clock
bricle Aug 25, 2025
44e3d05
boards: st: stm32h7s78_dk: Add PLL2 node and SDMMC1 node
bricle Aug 25, 2025
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12 changes: 12 additions & 0 deletions boards/ruiside/art_pi2/Kconfig.defconfig
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Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
# ART-Pi2 board configuration
#
# Copyright (c) 2025 Shan Pen <[email protected]>
#
# SPDX-License-Identifier: Apache-2.0

if DISK_DRIVER_SDMMC

config SDMMC_STM32_CLOCK_CHECK
default n

endif # DISK_DRIVER_SDMMC
24 changes: 24 additions & 0 deletions boards/ruiside/art_pi2/art_pi2.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,18 @@
status = "okay";
};

&pll2 {
div-m = <2>;
mul-n = <50>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
div-s = <4>;
div-t = <2>;
clocks = <&clk_hse>;
status = "okay";
};

&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(250)>;
Expand All @@ -98,6 +110,18 @@
status = "okay";
};

&sdmmc1 {
pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
&sdmmc1_d2_pc10 &sdmmc1_d3_pc11
&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
pinctrl-names = "default";
clk-div = <13>;
bus-width = <4>;
cd-gpios = <&gpion 7 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
disk-name = "SD";
status = "okay";
};

&rng {
status = "okay";
};
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7 changes: 7 additions & 0 deletions boards/st/stm32h7s78_dk/Kconfig.defconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -31,4 +31,11 @@ config STM32_LTDC_FB_USE_SHARED_MULTI_HEAP
default y
endif # DISPLAY

if DISK_DRIVER_SDMMC

config SDMMC_STM32_CLOCK_CHECK
default n

endif # DISK_DRIVER_SDMMC

endif # BOARD_STM32H7S78_DK
24 changes: 24 additions & 0 deletions boards/st/stm32h7s78_dk/stm32h7s78_dk.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -109,6 +109,18 @@
status = "okay";
};

&pll2 {
div-m = <2>;
mul-n = <50>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
div-s = <4>;
div-t = <2>;
clocks = <&clk_hse>;
status = "okay";
};

&pll3 {
div-m = <12>;
mul-n = <25>;
Expand Down Expand Up @@ -351,3 +363,15 @@ zephyr_udc0: &usb2 {};
def-back-color-green = <0xFF>;
def-back-color-blue = <0xFF>;
};

&sdmmc1 {
pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
&sdmmc1_d2_pc10 &sdmmc1_d3_pc11
&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
pinctrl-names = "default";
clk-div = <13>;
bus-width = <4>;
cd-gpios = <&gpiom 14 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
disk-name = "SD";
status = "okay";
};
20 changes: 20 additions & 0 deletions dts/arm/st/h7rs/stm32h7rs.dtsi
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Expand Up @@ -908,6 +908,26 @@
resets = <&rctl STM32_RESET(APB5, 1)>;
status = "disabled";
};

sdmmc1: sdmmc@52007000 {
compatible = "st,stm32-sdmmc";
reg = <0x52007000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB5, 8)>,
<&rcc STM32_SRC_PLL2_S SDMMC_SEL(0)>;
resets = <&rctl STM32_RESET(AHB5, 8)>;
interrupts = <108 0>;
status = "disabled";
};

sdmmc2: sdmmc@48002400 {
compatible = "st,stm32-sdmmc";
reg = <0x48002400 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 9)>,
<&rcc STM32_SRC_PLL2_S SDMMC_SEL(0)>;
resets = <&rctl STM32_RESET(AHB2, 9)>;
interrupts = <109 0>;
status = "disabled";
};
};

otgfs_phy: otgfs_phy {
Expand Down
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