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372ff54
dts: adi: max32: Move some devicetrees from arm to vendor
MaureenHelm Apr 19, 2024
045daf6
soc: adi: max32: Refactor clock control configuration
MaureenHelm May 17, 2024
8a0aa9d
soc: adi: max32: Add support for secondary risc-v core
MaureenHelm Apr 19, 2024
5ab431f
boards: adi: max32655evkit: Refactor devicetree common nodes
MaureenHelm May 13, 2024
77fe4a9
boards: adi: max32655evkit: Partition flash for arm and risc-v apps
MaureenHelm May 13, 2024
8059525
boards: adi: max32655evkit: Add support for risc-v core
MaureenHelm Apr 19, 2024
a43a366
samples: sysbuild: Enable hello world for max32655evkit board
MaureenHelm May 13, 2024
ab72375
dts: consolodate SRAM sections.
kevin-gillespie Feb 24, 2025
58f38d0
boards: common: Use correct RV32 interface path
petejohanson-adi Apr 30, 2025
e3e6ba9
dts: adi: Refactor MAX32 to split M4/RV32 elements
petejohanson-adi May 1, 2025
0b93fbd
soc: adi: max32: Add pinctrl setup for debugging RV32
petejohanson-adi May 1, 2025
2715173
soc: adi: max32: Add RV32 interrupt controller
petejohanson-adi May 1, 2025
a98b7ae
drivers: timer: Add MAX32 RV32 system timer
petejohanson-adi May 1, 2025
44ca4ab
boards: adi: Add RV32 support to MAX32690EVKit
petejohanson-adi May 1, 2025
bb00470
west: runners: openocd: Add flash-specific pre inits
petejohanson-adi May 1, 2025
40ae2e4
boards: common: RV32 target adjustments
petejohanson-adi May 1, 2025
6679fa1
soc: adi: max32: Allow flash + partition settings for RV32 boot
petejohanson-adi May 7, 2025
575da0f
soc: adi: max32: Add optional delay to RV32 boot
petejohanson-adi May 7, 2025
03d586c
dts: common: adi: Refactor MAX7800x to support RV32
petejohanson-adi May 7, 2025
0768be2
tests: kernel.common.stack_sentinel: Use RV32 illegal instruction
petejohanson-adi May 9, 2025
9e584d8
drivers: hwinfo: Disable MAX32 hwinfo driver on RV32 core.
petejohanson-adi May 27, 2025
00b7097
tests: debug: Properly panic the MAX32 RV32 for coredump testing.
petejohanson-adi May 29, 2025
55bcae2
drivers: serial: Disable async support on MAX32 RV32
petejohanson-adi May 30, 2025
d11a856
tests: subsys: secure_storage: Exclude max78002evkit/rv32
petejohanson-adi Jul 30, 2025
5cd044b
soc: adi: max32: Redefine some intrinsics to avoid missing FENCE
petejohanson-adi Oct 8, 2025
5d58fd0
spsc_pbuf: Include <soc.h> to use SoC specific adjustments.
petejohanson-adi Oct 8, 2025
f25ab9b
soc: adi: max32: Note that RV32 supports RAM funcs
petejohanson-adi Aug 21, 2025
f0c906a
west.yml: Bump ADI HAL to latest export
petejohanson-adi Oct 10, 2025
aacb19f
tests: drivers: flash: Only test MAX32 flash1 on max32690evkit
petejohanson-adi Oct 10, 2025
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2 changes: 1 addition & 1 deletion boards/adi/apard32690/apard32690_max32690_m4.dts
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@

/dts-v1/;

#include <adi/max32/max32690.dtsi>
#include <adi/max32/max32690-m4.dtsi>
#include <adi/max32/max32690-pinctrl.dtsi>
#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
#include <zephyr/dt-bindings/gpio/arduino-header-r3.h>
Expand Down
1 change: 1 addition & 0 deletions boards/adi/max32655evkit/Kconfig.max32655evkit
Original file line number Diff line number Diff line change
Expand Up @@ -5,3 +5,4 @@

config BOARD_MAX32655EVKIT
select SOC_MAX32655_M4 if BOARD_MAX32655EVKIT_MAX32655_M4
select SOC_MAX32655_RV32 if BOARD_MAX32655EVKIT_MAX32655_RV32
63 changes: 63 additions & 0 deletions boards/adi/max32655evkit/doc/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -154,10 +154,73 @@ Debugging
Please refer to the `Flashing`_ section and run the ``west debug`` command
instead of ``west flash``.

Dual Core Support
*****************

An experimental board configuration for the secondary RISC-V core can be found
in
:zephyr_file:`boards/adi/max32655evkit/max32655evkit_max32655_rv32_defconfig`.

It can boot Zephyr and print "hello world" to a RAM console, but it currently
has significant limitations:

- **Kernel timer**: The zero-riscy core doesn't implement a machine timer and we
have not yet implemented a Zephyr driver for a system-level timer peripheral
on this SoC, therefore kernel functions that take a :c:type:`k_timeout_t`
argument, such as :c:func:`k_sleep` are not expected to work.

- **Interrupts**: The zero-riscy core only allows enabling/disabling interrupts
globally and assumes there is an interrupt controller outside of the core. We
have not yet implemented support for a system-level interrupt controller,
therefore kernel interrupt services are not expected to work.

- **Peripheral drivers**: Without interrupts, the existing UART, GPIO, and
other peripheral drivers won't work.

The primary Arm core uses Kconfig options,
:kconfig:option:`CONFIG_MAX32_SECONDARY_RV32` and
:kconfig:option:`CONFIG_MAX32_SECONDARY_RV32_BOOT_ADDRESS`, to enable and
configure the boot address for the secondary RISC-V core. The devicetree chosen
node, ``zephyr,code-rv32-partition``, specifies the default value for the boot
address.

:zephyr:code-sample:`sysbuild_hello_world` supports building the Arm and RISC-V
images:

.. zephyr-app-commands::
:zephyr-app: samples/sysbuild/hello_world
:board: max32655evkit/max32655/m4
:west-args: -T sample.sysbuild.hello_world.max32655evkit_m4_rv32
:goals: build
:compact:

The build system hasn't yet been instrumented to merge the two images into one
combined image, so you can use :zephyr_file:`scripts/build/mergehex.py` to
merge them:

.. code-block:: console

$ python scripts/build/mergehex.py -o build/merged.hex \
build/hello_world/zephyr/zephyr.hex build/remote/zephyr/zephyr.hex

Likewise, west runners aren't aware of combined image, so you can use JLink to
program it to flash:

.. code-block:: console

$ JLinkExe -device MAX32655 -if SWD -speed 4000 -autoconnect 1

J-Link>loadfile build/merged.hex

References
**********

- `MAX32655EVKIT web page`_

- `zero-riscy user manual`_

.. _MAX32655EVKIT web page:
https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32655evkit.html#eb-overview

.. _zero-riscy user manual:
https://pulp-platform.org/docs/user_manual.pdf
105 changes: 105 additions & 0 deletions boards/adi/max32655evkit/max32655evkit.dtsi
Original file line number Diff line number Diff line change
@@ -0,0 +1,105 @@
/*
* Copyright (c) 2023-2024 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <adi/max32/max32655-pinctrl.dtsi>
#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>

/ {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;

/*
* Concatenate SRAM0(32KB), SRAM1(32KB) and SRAM2(48KB) for the M4
*/
m4_sram: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(112)>;
};

/*
* Use SRAM3(16KB) for the RV32
*/
rv32_sram: memory@2001c000 {
compatible = "mmio-sram";
reg = <0x2001c000 DT_SIZE_K(16)>;
};
};

leds {
compatible = "gpio-leds";

led1: led_1 {
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
label = "Red LED";
};

led2: led_2 {
gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
label = "Blue LED";
};
};

buttons {
compatible = "gpio-keys";

pb1: pb1 {
gpios = <&gpio0 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "SW2";
zephyr,code = <INPUT_KEY_0>;
};

pb2: pb2 {
gpios = <&gpio0 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "SW3";
zephyr,code = <INPUT_KEY_1>;
};

pb_wakeup: pb_wakeup {
gpios = <&gpio3 1
(GPIO_PULL_UP | GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>;
label = "Wakeup";
zephyr,code = <INPUT_KEY_WAKEUP>;
};
};

/* These aliases are provided for compatibility with samples */
aliases {
led0 = &led1;
led1 = &led2;
sw0 = &pb1;
sw1 = &pb2;
watchdog0 = &wdt0;
};
};

&uart0 {
pinctrl-0 = <&uart0a_tx_p0_1 &uart0a_rx_p0_0>;
pinctrl-names = "default";
current-speed = <115200>;
data-bits = <8>;
parity = "none";
};

&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

m4_partition: partition@10000000 {
label = "image-m4";
reg = <0x10000000 DT_SIZE_K(256)>;
};

rv32_partition: partition@10040000 {
label = "image-rv32";
reg = <0x10040000 DT_SIZE_K(256)>;
};
};
};
86 changes: 31 additions & 55 deletions boards/adi/max32655evkit/max32655evkit_max32655_m4.dts
Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,8 @@

/dts-v1/;

#include <adi/max32/max32655.dtsi>
#include <adi/max32/max32655-pinctrl.dtsi>
#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <adi/max32/max32655-m4.dtsi>
#include "max32655evkit.dtsi"

/ {
model = "Analog Devices MAX32655EVKIT";
Expand All @@ -18,64 +16,48 @@
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &sram2;
zephyr,flash = &flash0;
zephyr,sram = &m4_sram;
zephyr,flash = &m4_partition;
zephyr,code-rv32-partition = &rv32_partition;
};

leds {
compatible = "gpio-leds";
aliases {
spi-flash0 = &spi0_cs0_flash;
};
};

led1: led_1 {
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
label = "Red LED";
};
&cpu1 {
pinctrl-0 = <&rv_tck_p1_0 &rv_tms_p1_1 &rv_tdi_p1_2 &rv_tdo_p1_3>;
pinctrl-names = "default";
};

led2: led_2 {
gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
label = "Blue LED";
};
};
&led1 {
status = "okay";
};

buttons {
compatible = "gpio-keys";

pb1: pb1 {
gpios = <&gpio0 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "SW2";
zephyr,code = <INPUT_KEY_0>;
};

pb2: pb2 {
gpios = <&gpio0 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "SW3";
zephyr,code = <INPUT_KEY_1>;
};

pb_wakeup: pb_wakeup {
gpios = <&gpio3 1
(GPIO_PULL_UP | GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>;
label = "Wakeup";
zephyr,code = <INPUT_KEY_WAKEUP>;
};
};
&led2 {
status = "okay";
};

/* These aliases are provided for compatibility with samples */
aliases {
led0 = &led1;
led1 = &led2;
sw0 = &pb1;
sw1 = &pb2;
watchdog0 = &wdt0;
};
&pb1 {
status = "okay";
};

&pb2 {
status = "okay";
};

&pb_wakeup {
status = "okay";
};

&uart0 {
pinctrl-0 = <&uart0a_tx_p0_1 &uart0a_rx_p0_0>;
status = "okay";
pinctrl-names = "default";
current-speed = <115200>;
data-bits = <8>;
parity = "none";
status = "okay";
};

&clk_ipo {
Expand Down Expand Up @@ -123,12 +105,6 @@
status = "okay";
};

&spi0 {
status = "okay";
pinctrl-0 = <&spi0_mosi_p0_5 &spi0_miso_p0_6 &spi0_sck_p0_7 &spi0_ss0_p0_4>;
pinctrl-names = "default";
};

&w1 {
pinctrl-0 = <&owm_io_p0_6 &owm_pe_p0_7>;
pinctrl-names = "default";
Expand All @@ -151,10 +127,10 @@
};

&spi0 {
status = "okay";
pinctrl-0 = <&spi0_mosi_p0_5 &spi0_miso_p0_6 &spi0_sck_p0_7>;
pinctrl-names = "default";
cs-gpios = <&gpio0 4 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>;
status = "okay";

spi0_cs0_flash: w25q128@0 {
compatible = "jedec,spi-nor";
Expand Down
2 changes: 1 addition & 1 deletion boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -22,4 +22,4 @@ supported:
- w1
- flash
ram: 48
flash: 512
flash: 256
62 changes: 62 additions & 0 deletions boards/adi/max32655evkit/max32655evkit_max32655_rv32.dts
Original file line number Diff line number Diff line change
@@ -0,0 +1,62 @@
/*
* Copyright (c) 2023-2024 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/

/dts-v1/;

#include <adi/max32/max32655-rv32.dtsi>
#include "max32655evkit.dtsi"

/ {
model = "Analog Devices MAX32655EVKIT";
compatible = "adi,max32655evkit";

chosen {
zephyr,console = &uart3;
zephyr,shell-uart = &uart3;
zephyr,sram = &rv32_sram;
zephyr,flash = &rv32_partition;
};
};

&rv32_sys_timer {
status = "okay";
};

&clk_iso {
status = "okay";
};

/*
* ERTCO is required for counter RTC
*/
&clk_ertco {
status = "okay";
};

&gpio0 {
status = "okay";
};

&gpio1 {
status = "okay";
};

&gpio2 {
status = "okay";
};

&gpio3 {
status = "okay";
};

&uart3 {
pinctrl-0 = <&lpuartb_rx_p2_6 &lpuartb_tx_p2_7>;
status = "okay";
pinctrl-names = "default";
current-speed = <115200>;
data-bits = <8>;
parity = "none";
};
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