STM32: Replace HAL register operations

drivers/adc/adc_stm32.c

@@ -20,6 +20,7 @@
 #include <zephyr/init.h>
 #include <zephyr/toolchain.h>
 #include <soc.h>
+#include <stm32_bitops.h>
 #include <stm32_cache.h>
 #include <zephyr/pm/device.h>
 #include <zephyr/pm/policy.h>
@@ -565,11 +566,12 @@ static void adc_stm32_calibration_start(const struct device *dev, bool single_en
 		 */
 		if ((dev_id != 0x482UL) && (rev_id != 0x2001UL)) {
 			adc_stm32_enable(adc);
-			MODIFY_REG(adc->CR, ADC_CR_CALINDEX, 0x9UL << ADC_CR_CALINDEX_Pos);
+			stm32_reg_modify_bits(&adc->CR, ADC_CR_CALINDEX,
+					      0x9UL << ADC_CR_CALINDEX_Pos);
 			__DMB();
-			MODIFY_REG(adc->CALFACT2, 0xFFFFFF00UL, 0x03021100UL);
+			stm32_reg_modify_bits(&adc->CALFACT2, 0xFFFFFF00UL, 0x03021100UL);
 			__DMB();
-			SET_BIT(adc->CALFACT, ADC_CALFACT_LATCH_COEF);
+			stm32_reg_set_bits(&adc->CALFACT, ADC_CALFACT_LATCH_COEF);
 			adc_stm32_disable(adc);
 		}
 	}
@@ -865,11 +867,10 @@ static void set_reg_value(const struct device *dev, uint32_t reg,
 			  uint32_t shift, uint32_t mask, uint32_t value)
 {
 	const struct adc_stm32_cfg *config = dev->config;
-	ADC_TypeDef *adc = config->base;
-
-	uintptr_t addr = (uintptr_t)adc + reg;
+	size_t reg32_offset = reg / sizeof(uint32_t);
+	volatile uint32_t *addr = (volatile uint32_t *)config->base + reg32_offset;
 
-	MODIFY_REG(*(volatile uint32_t *)addr, (mask << shift), (value << shift));
+	stm32_reg_modify_bits(addr, mask << shift, value << shift);
 }
 
 static int set_resolution(const struct device *dev,

drivers/adc/adc_stm32wb0.c

@@ -46,6 +46,7 @@
 #include <zephyr/sys/math_extras.h>
 
 #include <soc.h>
+#include <stm32_bitops.h>
 #include <stm32_ll_adc.h>
 #include <stm32_ll_utils.h>
 
@@ -304,7 +305,7 @@ static inline void ll_adc_set_conversion_channel(ADC_TypeDef *ADCx,
 	const uint32_t reg = (Conversion & 8) ? 1 : 0;
 	const uint32_t shift = 4 * (Conversion & 7);
 
-	MODIFY_REG((&ADCx->SEQ_1)[reg], ADC_SEQ_1_SEQ0 << shift, Channel << shift);
+	stm32_reg_modify_bits((&ADCx->SEQ_1) + reg, ADC_SEQ_1_SEQ0 << shift, Channel << shift);
 }
 
 /**
@@ -379,7 +380,7 @@ static inline void ll_adc_set_calib_point_for_any(ADC_TypeDef *ADCx, uint32_t Ty
 
 	const uint32_t shift = (group_shift + type_shift);
 
-	MODIFY_REG(ADCx->COMP_SEL, (ADC_COMP_SEL_OFFSET_GAIN0 << shift), (Point << shift));
+	stm32_reg_modify_bits(&ADCx->COMP_SEL, ADC_COMP_SEL_OFFSET_GAIN0 << shift, Point << shift);
 }
 
 static void adc_acquire_pm_locks(void)

drivers/clock_control/clock_stm32_ll_common.c

@@ -6,6 +6,7 @@
  */
 
 #include <soc.h>
+#include <stm32_bitops.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_rcc.h>
@@ -75,12 +76,12 @@
 #endif
 
 #if defined(RCC_PLLCFGR_PLLPEN)
-#define RCC_PLLP_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)
+#define RCC_PLLP_ENABLE() stm32_reg_set_bits(&RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)
 #else
 #define RCC_PLLP_ENABLE()
 #endif /* RCC_PLLCFGR_PLLPEN */
 #if defined(RCC_PLLCFGR_PLLQEN)
-#define RCC_PLLQ_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)
+#define RCC_PLLQ_ENABLE() stm32_reg_set_bits(&RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)
 #else
 #define RCC_PLLQ_ENABLE()
 #endif /* RCC_PLLCFGR_PLLQEN */
@@ -820,11 +821,11 @@ static void set_up_plls(void)
 #if defined(STM32_PLL_ENABLED)
 
 #if defined(STM32_SRC_PLL_P) && STM32_PLL_P_ENABLED
-	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, pllp(STM32_PLL_P_DIVISOR));
+	stm32_reg_modify_bits(&RCC->PLLCFGR, RCC_PLLCFGR_PLLP, pllp(STM32_PLL_P_DIVISOR));
 	RCC_PLLP_ENABLE();
 #endif
 #if defined(STM32_SRC_PLL_Q) && STM32_PLL_Q_ENABLED
-	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, pllq(STM32_PLL_Q_DIVISOR));
+	stm32_reg_modify_bits(&RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, pllq(STM32_PLL_Q_DIVISOR));
 	RCC_PLLQ_ENABLE();
 #endif
 

drivers/clock_control/clock_stm32_ll_mp13.c

@@ -5,6 +5,7 @@
  */
 
 #include <soc.h>
+#include <stm32_bitops.h>
 
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
@@ -236,19 +237,20 @@ static int stm32_clock_control_init(const struct device *dev)
 	/* while active.*/
 
 	LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_HSE);
-	while ((READ_BIT(RCC->MPCKSELR, RCC_MPCKSELR_MPUSRCRDY) != RCC_MPCKSELR_MPUSRCRDY)) {
+	while (stm32_reg_read_bits(&RCC->MPCKSELR, RCC_MPCKSELR_MPUSRCRDY) !=
+	       RCC_MPCKSELR_MPUSRCRDY) {
 	}
 
-	CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN);
-	while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN) == RCC_PLL1CR_DIVPEN) {
+	stm32_reg_clear_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVPEN);
+	while (stm32_reg_read_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVPEN) == RCC_PLL1CR_DIVPEN) {
 	};
 
-	CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVQEN);
-	while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVQEN) == RCC_PLL1CR_DIVQEN) {
+	stm32_reg_clear_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVQEN);
+	while (stm32_reg_read_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVQEN) == RCC_PLL1CR_DIVQEN) {
 	};
 
-	CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVREN);
-	while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVREN) == RCC_PLL1CR_DIVREN) {
+	stm32_reg_clear_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVREN);
+	while (stm32_reg_read_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVREN) == RCC_PLL1CR_DIVREN) {
 	};
 
 	uint32_t pll1_n = DT_PROP(DT_NODELABEL(pll1), mul_n);
@@ -273,8 +275,8 @@ static int stm32_clock_control_init(const struct device *dev)
 	while (LL_RCC_PLL1_IsReady() != 1) {
 	}
 
-	SET_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN);
-	while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN) != RCC_PLL1CR_DIVPEN) {
+	stm32_reg_set_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVPEN);
+	while (stm32_reg_read_bits(&RCC->PLL1CR, RCC_PLL1CR_DIVPEN) != RCC_PLL1CR_DIVPEN) {
 	};
 
 	LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_PLL1);

drivers/clock_control/clock_stm32_ll_u5.c

@@ -8,6 +8,7 @@
 
 
 #include <soc.h>
+#include <stm32_bitops.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_rcc.h>
@@ -637,17 +638,17 @@ static int set_up_plls(void)
 
 	if (IS_ENABLED(STM32_PLL2_P_ENABLED)) {
 		LL_RCC_PLL2_SetP(STM32_PLL2_P_DIVISOR);
-		SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN);
+		stm32_reg_set_bits(&RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN);
 	}
 
 	if (IS_ENABLED(STM32_PLL2_Q_ENABLED)) {
 		LL_RCC_PLL2_SetQ(STM32_PLL2_Q_DIVISOR);
-		SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN);
+		stm32_reg_set_bits(&RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN);
 	}
 
 	if (IS_ENABLED(STM32_PLL2_R_ENABLED)) {
 		LL_RCC_PLL2_SetR(STM32_PLL2_R_DIVISOR);
-		SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN);
+		stm32_reg_set_bits(&RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN);
 	}
 
 	LL_RCC_PLL2_Enable();
@@ -689,17 +690,17 @@ static int set_up_plls(void)
 
 	if (IS_ENABLED(STM32_PLL3_P_ENABLED)) {
 		LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR);
-		SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN);
+		stm32_reg_set_bits(&RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN);
 	}
 
 	if (IS_ENABLED(STM32_PLL3_Q_ENABLED)) {
 		LL_RCC_PLL3_SetQ(STM32_PLL3_Q_DIVISOR);
-		SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN);
+		stm32_reg_set_bits(&RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN);
 	}
 
 	if (IS_ENABLED(STM32_PLL3_R_ENABLED)) {
 		LL_RCC_PLL3_SetR(STM32_PLL3_R_DIVISOR);
-		SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN);
+		stm32_reg_set_bits(&RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN);
 	}
 
 	LL_RCC_PLL3_Enable();
@@ -905,11 +906,12 @@ int stm32_clock_control_init(const struct device *dev)
 	/* Disable unused clocks that are enabled (e.g. by bootloader or as wakeup source).
 	 * These will not be enabled, unless the MCU uses them for PM wakeup purposes.
 	 */
-	if (!IS_ENABLED(STM32_MSIS_ENABLED) && (READ_BIT(RCC->CR, RCC_CR_MSISON) != 0U)) {
+	if (!IS_ENABLED(STM32_MSIS_ENABLED) &&
+	    (stm32_reg_read_bits(&RCC->CR, RCC_CR_MSISON) != 0U)) {
 		LL_RCC_MSIS_Disable();
 	}
 
-	if (!IS_ENABLED(STM32_HSI_ENABLED) && (READ_BIT(RCC->CR, RCC_CR_HSION) != 0U)) {
+	if (!IS_ENABLED(STM32_HSI_ENABLED) && (stm32_reg_read_bits(&RCC->CR, RCC_CR_HSION) != 0U)) {
 		LL_RCC_HSI_Disable();
 	}
 #endif

drivers/clock_control/clock_stm32f2_f4_f7.c

@@ -7,6 +7,7 @@
 
 
 #include <soc.h>
+#include <stm32_bitops.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_rcc.h>
@@ -97,7 +98,7 @@ __unused
 void config_pll_sysclock(void)
 {
 #if defined(STM32_SRC_PLL_R) && STM32_PLL_R_ENABLED && defined(RCC_PLLCFGR_PLLR)
-	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, pllr(STM32_PLL_R_DIVISOR));
+	stm32_reg_modify_bits(&RCC->PLLCFGR, RCC_PLLCFGR_PLLR, pllr(STM32_PLL_R_DIVISOR));
 #endif
 	LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
 				    pllm(STM32_PLL_M_DIVISOR),

drivers/counter/counter_ll_stm32_rtc.c

@@ -18,6 +18,7 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/kernel.h>
 #include <soc.h>
+#include <stm32_bitops.h>
 #include <stm32_ll_cortex.h>
 #include <stm32_ll_exti.h>
 #include <stm32_ll_pwr.h>
@@ -270,46 +271,46 @@ static int rtc_stm32_deinit(void)
 	}
 
 #if defined(CONFIG_SOC_SERIES_STM32F1X)
-	WRITE_REG(RTC->CNTL, 0U);
-	WRITE_REG(RTC->CNTH, 0U);
-	WRITE_REG(RTC->PRLH, 0U);
-	WRITE_REG(RTC->PRLL, 0x8000U);
-	WRITE_REG(RTC->CRH, 0U);
-	WRITE_REG(RTC->CRL, 0x20U);
+	stm32_reg_write(&RTC->CNTL, 0U);
+	stm32_reg_write(&RTC->CNTH, 0U);
+	stm32_reg_write(&RTC->PRLH, 0U);
+	stm32_reg_write(&RTC->PRLL, 0x8000U);
+	stm32_reg_write(&RTC->CRH, 0U);
+	stm32_reg_write(&RTC->CRL, 0x20U);
 #else /* CONFIG_SOC_SERIES_STM32F1X */
-	WRITE_REG(RTC->CR, 0U);
-	WRITE_REG(RTC->TR, 0U);
+	stm32_reg_write(&RTC->CR, 0U);
+	stm32_reg_write(&RTC->TR, 0U);
 #ifdef RTC_WUTR_WUT
-	WRITE_REG(RTC->WUTR, RTC_WUTR_WUT);
+	stm32_reg_write(&RTC->WUTR, RTC_WUTR_WUT);
 #endif /* RTC_WUTR_WUT */
-	WRITE_REG(RTC->DR, RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0);
-	WRITE_REG(RTC->PRER, RTC_PRER_PREDIV_A | 0xFFU);
-	WRITE_REG(RTC->ALRMAR, 0U);
+	stm32_reg_write(&RTC->DR, RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0);
+	stm32_reg_write(&RTC->PRER, RTC_PRER_PREDIV_A | 0xFFU);
+	stm32_reg_write(&RTC->ALRMAR, 0U);
 #ifdef RTC_CR_ALRBE
-	WRITE_REG(RTC->ALRMBR, 0U);
+	stm32_reg_write(&RTC->ALRMBR, 0U);
 #endif /* RTC_CR_ALRBE */
 
 #if HW_SUBSECOND_SUPPORT
-	WRITE_REG(RTC->CALR, 0U);
-	WRITE_REG(RTC->SHIFTR, 0U);
-	WRITE_REG(RTC->ALRMASSR, 0U);
+	stm32_reg_write(&RTC->CALR, 0U);
+	stm32_reg_write(&RTC->SHIFTR, 0U);
+	stm32_reg_write(&RTC->ALRMASSR, 0U);
 #ifdef RTC_CR_ALRBE
-	WRITE_REG(RTC->ALRMBSSR, 0U);
+	stm32_reg_write(&RTC->ALRMBSSR, 0U);
 #endif /* RTC_CR_ALRBE */
 #endif /* HW_SUBSECOND_SUPPORT */
 
 #if defined(RTC_PRIVCFGR_PRIV)
-	WRITE_REG(RTC->PRIVCFGR, 0U);
+	stm32_reg_write(&RTC->PRIVCFGR, 0U);
 #endif /* RTC_PRIVCFGR_PRIV */
 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-	WRITE_REG(RTC->SECCFGR,  0U);
+	stm32_reg_write(&RTC->SECCFGR,  0U);
 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
 
 	/* Reset I(C)SR register and exit initialization mode */
 #ifdef RTC_ICSR_INIT
-	WRITE_REG(RTC->ICSR, 0U);
+	stm32_reg_write(&RTC->ICSR, 0U);
 #else
-	WRITE_REG(RTC->ISR, 0U);
+	stm32_reg_write(&RTC->ISR, 0U);
 #endif
 
 #endif /* CONFIG_SOC_SERIES_STM32F1X */

drivers/entropy/entropy_stm32.c

@@ -17,6 +17,7 @@
 #include <errno.h>
 #include <soc.h>
 #include <zephyr/pm/policy.h>
+#include <stm32_bitops.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_rcc.h>
 #include <stm32_ll_rng.h>
@@ -209,9 +210,9 @@ static void configure_rng(void)
 	 * The RNG clock must be 48MHz else the clock DIV is not adpated.
 	 * The RNG_CR_CONDRST is set to 1 at the same time the RNG_CR is written
 	 */
-	cur_nist_cfg = READ_BIT(rng->CR,
-				(RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1 |
-				RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3
+	cur_nist_cfg = stm32_reg_read_bits(&rng->CR,
+					   (RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1 |
+					    RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3
 #if defined(RNG_CR_ARDIS)
 				| RNG_CR_ARDIS
 	/* For STM32U5 series, the ARDIS bit7 is considered in the nist-config */
@@ -224,7 +225,7 @@ static void configure_rng(void)
 #endif /* health_test_config */
 
 	if (cur_nist_cfg != desired_nist_cfg || cur_htcr != desired_htcr) {
-		MODIFY_REG(rng->CR, cur_nist_cfg, (desired_nist_cfg | RNG_CR_CONDRST));
+		stm32_reg_modify_bits(&rng->CR, cur_nist_cfg, desired_nist_cfg | RNG_CR_CONDRST);
 
 #if DT_INST_NODE_HAS_PROP(0, health_test_config)
 #if DT_INST_NODE_HAS_PROP(0, health_test_magic)

drivers/entropy/entropy_stm32.h

@@ -5,6 +5,7 @@
  */
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
+#include <stm32_bitops.h>
 #include <stm32_ll_rng.h>
 
 /**
@@ -109,7 +110,7 @@ static inline rng_sample_t ll_rng_read_rand_data(RNG_TypeDef *RNGx)
 	 * Raw register access is performed because STM32CubeWB0 v1.0.0
 	 * package is lacking the LL function to clear IRQ flags.
 	 */
-	WRITE_REG(RNG->IRQ_SR, RNG_IRQ_SR_FF_FULL_IRQ);
+	stm32_reg_write(&RNGx->IRQ_SR, RNG_IRQ_SR_FF_FULL_IRQ);
 
 	return rnd;
 #elif defined(CONFIG_SOC_SERIES_STM32WB0X)

drivers/flash/flash_stm32_ospi.c

@@ -13,6 +13,7 @@
 #include <zephyr/arch/common/ffs.h>
 #include <zephyr/sys/util.h>
 #include <soc.h>
+#include <stm32_bitops.h>
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/drivers/clock_control.h>
@@ -1139,9 +1140,8 @@ static bool stm32_ospi_is_memorymap(const struct device *dev)
 {
 	struct flash_stm32_ospi_data *dev_data = dev->data;
 
-	return ((READ_BIT(dev_data->hospi.Instance->CR,
-			  OCTOSPI_CR_FMODE) == OCTOSPI_CR_FMODE) ?
-			  true : false);
+	return stm32_reg_read_bits(&dev_data->hospi.Instance->CR, OCTOSPI_CR_FMODE) ==
+	       OCTOSPI_CR_FMODE;
 }
 
 static int stm32_ospi_abort(const struct device *dev)