Enabling ZC143 Display Support on the MIMXRT700_EVK

boards/nxp/mimxrt700_evk/board.c

@@ -544,6 +544,48 @@
 	CLOCK_EnableClock(kCLOCK_Acmp0);
 	RESET_ClearPeripheralReset(kACMP0_RST_SHIFT_RSTn);
 #endif
+
+//@HARDCODE @INCOMPLETE(Emilio): Force hardcode for testing
+#if 1
+//@NOTE(Emilio): BOARD_InitMipiDsiClock
+    POWER_DisablePD(kPDRUNCFG_PPD_MIPIDSI);
+    POWER_DisablePD(kPDRUNCFG_APD_MIPIDSI);
+    POWER_DisablePD(kPDRUNCFG_PD_VDD2_MIPI);
+    POWER_ApplyPD();
+
+    /* Use PLL PFD1 as clock source, 396m. */
+    CLOCK_AttachClk(kMAIN_PLL_PFD1_to_MIPI_DPHYESC_CLK);
+    /* RxClkEsc min 60MHz, TxClkEsc 12 to 20MHz. */
+    /* RxClkEsc = 396MHz / 6 = 66MHz. */
+    CLOCK_SetClkDiv(kCLOCK_DivDphyEscRxClk, 6);
+    /* TxClkEsc = 396MHz / 6 / 4 = 16.5MHz. */
+    CLOCK_SetClkDiv(kCLOCK_DivDphyEscTxClk, 4);
+
+    CLOCK_InitAudioPfd(kCLOCK_Pfd2, 30);
+
+    CLOCK_AttachClk(kAUDIO_PLL_PFD2_to_MIPI_DSI_HOST_PHY);
+
+    CLOCK_SetClkDiv(kCLOCK_DivDphyClk, 1);
+
+
+//@NOTE(Emilio): BOARD_InitLcdifPowerReset
+    POWER_DisablePD(kPDRUNCFG_SHUT_MEDIA_MAINCLK);
+    POWER_DisablePD(kPDRUNCFG_APD_LCDIF);
+    POWER_DisablePD(kPDRUNCFG_PPD_LCDIF);
+    POWER_ApplyPD();
+
+    CLOCK_EnableClock(kCLOCK_Lcdif);
+    RESET_ClearPeripheralReset(kLCDIF_RST_SHIFT_RSTn);
+
+
+//@NOTE(Emilio): Clock code in BOARD_InitLcdif
+    CLOCK_InitMainPfd(kCLOCK_Pfd2, 17);
+    CLOCK_SetClkDiv(kCLOCK_DivMediaMainClk, 2U);
+    CLOCK_AttachClk(kMAIN_PLL_PFD2_to_MEDIA_MAIN);
+
+
+#endif
+
 }
 
 static void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx)

boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi

@@ -193,4 +193,56 @@
 			slew-rate = "normal";
 		};
 	};
+
+	pinmux_display: pinmux_display {
+		group0 {
+			pinmux = <XSPI2_PCS_A_0_PIO4_0>,
+				<XSPI2_DATA0_PIO4_1>,
+				<XSPI2_DATA1_PIO4_2>,
+				<XSPI2_DATA2_PIO4_3>,
+				<XSPI2_DATA3_PIO4_4>,
+				<XSPI2_DQS_A_0_PIO4_5>,
+				<XSPI2_DATA4_PIO4_6>,
+				<XSPI2_DATA5_PIO4_7>,
+				<XSPI2_DATA6_PIO4_8>,
+				<XSPI2_DATA7_PIO4_9>,
+				<XSPI2_SCK_A_PIO4_10>,
+				<XSPI2_SCK_A_N_PIO4_11>,
+				<XSPI2_DATA8_PIO4_12>,
+				<XSPI2_DATA9_PIO4_13>,
+				<XSPI2_DATA10_PIO4_14>,
+				<XSPI2_DATA11_PIO4_15>,
+				<XSPI2_DQS_A_1_PIO4_16>,
+				<XSPI2_DATA12_PIO4_17>,
+				<XSPI2_DATA13_PIO4_18>,
+				<XSPI2_DATA14_PIO4_19>,
+				<XSPI2_DATA15_PIO4_20>;
+			drive-strength = "normal";
+			slew-rate = "normal";
+			input-enable;
+		};
+
+		group1 {
+			pinmux = <GPIO1_GPIO10_PIO1_10>,
+				<GPIO1_GPIO14_PIO1_14>,
+				<GPIO3_GPIO4_PIO3_4>,
+				<GPIO3_GPIO5_PIO3_5>;
+			drive-strength = "normal";
+			slew-rate = "normal";
+		};
+
+		/*
+			@INCOMPLETE(Emilio): Each mux takes different flags.
+				Place into seperate groups
+		group2 {
+			pinmux = <LP_FLEXCOMM8_P0_PIO0_6>,
+				<LP_FLEXCOMM8_P1_PIO0_7>,
+				<GPIO1_GPIO13_PIO1_13>,
+				<GPIO3_GPIO8_PIO3_8>;
+			drive-strength = "normal";
+			slew-rate = "normal";
+		};
+		*/
+
+	};
 };

boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts

@@ -403,7 +403,7 @@ zephyr_udc0: &usb0 {
 	pinctrl-names = "default";
 };
 
-p3t1755dp_ard_i2c_interface: &flexcomm8_lpi2c8 {};
+//p3t1755dp_ard_i2c_interface: &flexcomm8_lpi2c8 {};
 
 &rtc0 {
 	status = "okay";
@@ -421,6 +421,3 @@ p3t1755dp_ard_i2c_interface: &flexcomm8_lpi2c8 {};
 	status = "okay";
 };
 
-&pca9422 {
-	status = "okay";
-};

boards/shields/zc143ac72mipi/Kconfig.defconfig

@@ -0,0 +1,20 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SHIELD_ZC143AC72MIPI
+if LVGL
+
+# Enable double buffering
+# config LV_Z_DOUBLE_VDB
+#	default y
+
+# config LV_Z_BITS_PER_PIXEL
+#	default 16
+
+endif # LVGL
+
+if INPUT
+# config ---
+endif # INPUT
+
+endif # SHIELD_ZC143AC72MIPI

boards/shields/zc143ac72mipi/Kconfig.shield

@@ -0,0 +1,5 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SHIELD_ZC143AC72MIPI
+	def_bool $(shields_list_contains,zc143ac72mipi)

boards/shields/zc143ac72mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf

@@ -0,0 +1,2 @@
+CONFIG_REGULATOR=y
+CONFIG_DCACHE=n

boards/shields/zc143ac72mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay

@@ -0,0 +1,18 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
+#include <zephyr/dt-bindings/display/panel.h>
+
+&zephyr_lcdif {
+	status = "okay";
+	clock-frequency = <279000000>;
+	wr-period = <14>;
+	wr-assert = <6>;
+	wr-deassert = <13>;
+	cs-assert = <1>;
+	cs-deassert = <4>;
+};

boards/shields/zc143ac72mipi/doc/index.rst

@@ -0,0 +1,2 @@
+#EMPTY DOC FOR NOW
+

boards/shields/zc143ac72mipi/shield.yml

@@ -0,0 +1,6 @@
+shields:
+  - name: zc143ac72mipi
+    full_name: --- ZC143AC72 MIPI LCD Module
+    vendor: ---
+    supported_features:
+      - display

boards/shields/zc143ac72mipi/zc143ac72mipi.overlay

@@ -0,0 +1,73 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,display = &co5300_zc143ac72mipi;
+//		zephyr,touch = &tma525b_zc143ac72mipi;
+	};
+
+	/*
+	en_mipi_display_g1120b0mipi: enable-mipi-display {
+		compatible = "regulator-fixed";
+		regulator-name = "en_mipi_display";
+		enable-gpio = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
+		regulator-boot-on;
+	};
+
+	lvgl_pointer {
+		compatible = "zephyr,lvgl-pointer-input";
+		input = <&ft3267_zc143ac72mipi>;
+		display = <&co5300_zc143ac72mipi>;
+		invert-y;
+	};
+	*/
+};
+/*
+&nxp_mipi_i2c {
+	status = "okay";
+
+	tma525b_zc143ac72mipi: tma525b@24 {
+		/*
+		 * Note- the actual controller present on this IC is a FT3267,
+		 * but the FT35336 driver in Zephyr supports this IC.
+		 */
+		 /*
+		compatible = "focaltech,tma525b";
+		reg = <0x24>;
+		int-gpio = <&nxp_mipi_connector 29 GPIO_ACTIVE_LOW>;
+		reset-gpio = <&nxp_mipi_connector 28 GPIO_ACTIVE_LOW>;
+	};
+};
+*/
+
+&zephyr_mipi_dsi {
+	status = "okay";
+	autoinsert-eotp;
+	phy-clock = <319488000>;
+
+	co5300_zc143ac72mipi: co5300@0 {
+		status = "okay";
+		compatible = "chipone,co5300";
+		reg = <0x0>;
+		reset-gpios = <&nxp_mipi_connector 21 GPIO_ACTIVE_HIGH>;
+		backlight-gpios = <&nxp_mipi_connector 34 GPIO_ACTIVE_HIGH>;
+		tear-effect-gpios = <&nxp_mipi_connector 22 GPIO_ACTIVE_HIGH>;
+		power-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
+		data-lanes = <1>;
+		width = <466>;
+		height = <466>;
+		pixel-format = <MIPI_DSI_PIXFMT_RGB565>;
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};

drivers/display/CMakeLists.txt

@@ -43,6 +43,7 @@ zephyr_library_sources_ifdef(CONFIG_RENESAS_RA_GLCDC		display_renesas_ra.c)
 zephyr_library_sources_ifdef(CONFIG_ILI9806E_DSI		display_ili9806e_dsi.c)
 zephyr_library_sources_ifdef(CONFIG_ST7701 display_st7701.c)
 zephyr_library_sources_ifdef(CONFIG_LPM013M126 display_lpm013m126.c)
+zephyr_library_sources_ifdef(CONFIG_CO5300 display_co5300.c)
 
 zephyr_library_sources_ifdef(CONFIG_MICROBIT_DISPLAY
 	mb_display.c

drivers/display/Kconfig

@@ -60,5 +60,6 @@ source "drivers/display/Kconfig.renesas_ra"
 source "drivers/display/Kconfig.ili9806e_dsi"
 source "drivers/display/Kconfig.st7701"
 source "drivers/display/Kconfig.lpm013m126"
+source "drivers/display/Kconfig.co5300"
 
 endif # DISPLAY

drivers/display/Kconfig.co5300

@@ -0,0 +1,15 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+
+config CO5300
+	bool "MCUX ---"
+	default y
+	select MIPI_DSI
+	depends on DT_HAS_CHIPONE_CO5300_ENABLED
+	help
+	  ---
+
+
+if CO5300
+endif # CO5300