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13 changes: 13 additions & 0 deletions boards/st/stm32u083c_dk/stm32u083c_dk.dts
Original file line number Diff line number Diff line change
Expand Up @@ -175,3 +175,16 @@ stm32_lp_tick_source: &lptim2 {
};
};
};

zephyr_udc0: &usb {
clocks = <&rcc STM32_CLOCK(APB1, 13)>,
<&rcc STM32_SRC_HSI48 CLK48_SEL(3)>;
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Probably should be described as a st,stm32-clock-mux like done on STM32F4 (see stm32f412.dtsi).

See also: #96353

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I think it is a good idea. I prepared some implementation, but it is not fully working yet.
I'm a bit confused how it works on STM32F412, since I see there is e.g. following code in clock_stm32_ll_common.c file:

#if defined(STM32_CK48_ENABLED)
	case STM32_SRC_CK48:
		*rate = get_ck48_frequency();
		break;
#endif /* STM32_CK48_ENABLED */

But I couldn't find any place where the macro STM32_CK48_ENABLED would be defined.
Either I'm missing something, or the code is actually not used on STM32F412.
However, the example for nucleo_f412zg board works on my side.

pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};

&clk_hsi48 {
status = "okay";
crs-usb-sof;
};
7 changes: 0 additions & 7 deletions dts/arm/st/u0/stm32u0.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -77,13 +77,6 @@
status = "disabled";
};

clk_hsi48: clk-hsi48 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(48)>;
status = "disabled";
};

clk_msi: clk-msi {
#clock-cells = <0>;
compatible = "st,stm32-msi-clock";
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9 changes: 9 additions & 0 deletions dts/arm/st/u0/stm32u073.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,15 @@
};
};

clocks {
clk_hsi48: clk-hsi48 {
#clock-cells = <0>;
compatible = "st,stm32-hsi48-clock";
clock-frequency = <DT_FREQ_M(48)>;
status = "disabled";
};
};

sram1: memory@20000000 {
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM1";
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