riscv: add Smcsrind indirect CSR access extension support #97560
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zephyrbot
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area: Architectures
area: RISCV
zephyrbot
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VynDragon,
dcpleung,
edersondisouza,
fkokosinski,
katsuster,
kgugala,
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mgielda,
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npitre,
tgorochowik and
ycsin
ruuddw
reviewed
Oct 16, 2025
Add support for the RISC-V Smcsrind extension, which provides indirect access to CSRs through the MISELECT and MIREG registers. Changes: - Added CONFIG_RISCV_ISA_EXT_SMCSRIND Kconfig option - Implemented 4 helper functions for indirect CSR access: * icsr_read/write - basic access * icsr_read_set/clear - bit manipulation - Defined 7 CSR registers (MISELECT, MIREG, MIREG2-6) This is a CSR-only extension that does not require any compiler support or march flags. The helper functions compile to standard CSR instructions and work with any toolchain that supports Zicsr. Primary use case: RISC-V AIA (Advanced Interrupt Architecture) uses indirect CSRs to access IMSIC (Incoming MSI Controller) registers. Signed-off-by: Afonso Oliveira <[email protected]>
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Thanks for the review @ruuddw. All the changes requested are addressed! |
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ruuddw
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Oct 17, 2025
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@kgugala @fkokosinski @tgorochowik Just a friendly ping :) |
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Add support for the RISC-V Smcsrind extension, which provides access to iCSRs through the MISELECT and MIREG registers.
Changes:
This is a CSR-only extension that does not require any compiler support or march flags. The helper functions compile to standard CSR instructions and work with any toolchain that supports Zicsr.
Primary use case: RISC-V AIA (Advanced Interrupt Architecture) uses indirect CSRs to access IMSIC (Incoming MSI Controller) registers. Relates to upstreaming AIA as described in #82487.