drivers: reset: microchip: Add G1 reset driver

boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.yaml

@@ -11,6 +11,7 @@ flash: 1024
 ram: 256
 supported:
   - pinctrl
+  - reset
   - shell
   - uart
 vendor: microchip

drivers/reset/CMakeLists.txt

@@ -15,4 +15,5 @@ zephyr_library_sources_ifdef(CONFIG_RESET_NXP_MRCC reset_nxp_mrcc.c)
 zephyr_library_sources_ifdef(CONFIG_RESET_NXP_RSTCTL reset_nxp_rstctl.c)
 zephyr_library_sources_ifdef(CONFIG_RESET_MMIO reset_mmio.c)
 zephyr_library_sources_ifdef(CONFIG_RESET_MCHP_MSS reset_mchp_mss.c)
+zephyr_library_sources_ifdef(CONFIG_RESET_MCHP_RSTC_G1 reset_mchp_rstc_g1.c)
 zephyr_library_sources_ifdef(CONFIG_RESET_SF32LB reset_sf32lb.c)

drivers/reset/Kconfig

@@ -38,6 +38,7 @@ rsource "Kconfig.lpc_syscon"
 rsource "Kconfig.nxp_mrcc"
 rsource "Kconfig.nxp_rstctl"
 rsource "Kconfig.mmio"
+rsource "Kconfig.mchp"
 rsource "Kconfig.mchp_mss"
 rsource "Kconfig.sf32lb"
 

drivers/reset/Kconfig.mchp

@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config RESET_MCHP_RSTC_G1
+	bool "Microchip Reset Controller g1 peripheral driver"
+	default y
+	depends on DT_HAS_MICROCHIP_RSTC_G1_RESET_ENABLED
+	help
+	  Enable RESET driver for Microchip G1.

drivers/reset/reset_mchp_rstc_g1.c

@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file reset_mchp_rstc_g1.c
+ * @brief Zephyr reset driver for Microchip G1 peripherals
+ *
+ * This file implements the driver for the Microchip RSTC g1 reset controller,
+ * providing APIs to assert, deassert, toggle, and query the status of reset lines.
+ *
+ */
+
+#include <zephyr/init.h>
+#include <soc.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/reset.h>
+
+#define DT_DRV_COMPAT microchip_rstc_g1_reset
+
+/* Maximum number of reset lines supported by the controller */
+#define MCHP_RST_LINE_MAX 8
+
+struct reset_mchp_config {
+	rstc_registers_t *regs;
+};
+
+/**
+ * @brief Get the status of a reset line.
+ *
+ * This function checks if the specified reset line is currently asserted.
+ *
+ * @param[in]  dev	Pointer to the device structure for the driver instance.
+ * @param[in]  id	 Reset line ID (0-7).
+ * @param[out] status Pointer to a variable to store the status (1 = asserted, 0 = not asserted).
+ *
+ * @retval 0		On success.
+ * @retval -EINVAL  If the reset line ID is invalid.
+ */
+static int reset_mchp_status(const struct device *dev, uint32_t id, uint8_t *status)
+{
+	int ret = 0;
+	uint8_t rcause = 0;
+
+	if (id >= MCHP_RST_LINE_MAX) {
+		ret = -EINVAL;
+	} else {
+		rcause = (((const struct reset_mchp_config *)((dev)->config))->regs)->RSTC_RCAUSE;
+		*status = (rcause & BIT(id)) ? 1 : 0;
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Assert (activate) a reset line.
+ *
+ * This function asserts the specified reset line.
+ *
+ * @param[in] dev Pointer to the device structure for the driver instance.
+ * @param[in] id  Reset line ID.
+ *
+ * @retval -ENOTSUP Operation not supported by hardware.
+ */
+static int reset_mchp_line_assert(const struct device *dev, uint32_t id)
+{
+	return -ENOTSUP;
+}
+
+/**
+ * @brief Deassert (deactivate) a reset line.
+ *
+ * This function deasserts the specified reset line.
+ *
+ * @param[in] dev Pointer to the device structure for the driver instance.
+ * @param[in] id  Reset line ID.
+ *
+ * @retval -ENOTSUP Operation not supported by hardware.
+ */
+static int reset_mchp_line_deassert(const struct device *dev, uint32_t id)
+{
+	return -ENOTSUP;
+}
+
+/**
+ * @brief Toggle a reset line (assert then deassert).
+ *
+ * This function asserts and then deasserts the specified reset line, with a short delay in between.
+ *
+ * @param[in] dev Pointer to the device structure for the driver instance.
+ * @param[in] id  Reset line ID.
+ *
+ * @retval -ENOTSUP Operation not supported by hardware.
+ */
+static int reset_mchp_line_toggle(const struct device *dev, uint32_t id)
+{
+	return -ENOTSUP;
+}
+
+static DEVICE_API(reset, reset_mchp_api) = {
+	.status = reset_mchp_status,
+	.line_assert = reset_mchp_line_assert,
+	.line_deassert = reset_mchp_line_deassert,
+	.line_toggle = reset_mchp_line_toggle,
+};
+
+/* Configuration instance for the Microchip RSTC g1 reset controller */
+static const struct reset_mchp_config reset_mchp_config = {
+	.regs = (rstc_registers_t *)DT_INST_REG_ADDR(0),
+};
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1,
+	     "Only one Microchip RSTC g1 instance is supported.");
+
+DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, &reset_mchp_config, PRE_KERNEL_1,
+		      CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &reset_mchp_api)

dts/arm/microchip/sam/sam_d5x_e5x/common/samd5xe5x.dtsi

@@ -54,6 +54,12 @@
 			};
 		};
 
+		rstc: rstc@40000c00 {
+			compatible = "microchip,rstc-g1-reset";
+			status = "disabled";
+			reg = <0x40000c00 0x400>;
+		};
+
 		sercom0: sercom@40003000 {
 			compatible = "microchip,sercom-g1";
 			status = "disabled";

dts/bindings/reset/microchip,rstc-g1-reset.yaml

@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+title: Microchip RSTC Reset driver
+
+description: |
+  Microchip RSTC Reset driver bindings.
+
+  Group g1 RSTC Reset driver supports following hardware peripherals:
+    - module name="RSTC" id="U2239" version="4.0.0"
+
+include: base.yaml
+
+compatible: "microchip,rstc-g1-reset"
+
+properties:
+  reg:
+    required: true
+    description: |
+      Base address and size of the RSTC register block.

include/zephyr/drivers/reset/mchp_reset.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/**
+ * @file mchp_reset.h
+ * @brief Microchip Reset header
+ *
+ * This header defines the macros for use with the Microchip reset controller driver.
+ */
+
+#ifndef INCLUDE_ZEPHYR_DRIVERS_RESET_MCHP_RESET_H_
+#define INCLUDE_ZEPHYR_DRIVERS_RESET_MCHP_RESET_H_
+
+#if defined(CONFIG_RESET_MCHP_RSTC_G1)
+#include "mchp_rstc_g1.h"
+#endif
+
+#endif /* INCLUDE_ZEPHYR_DRIVERS_RESET_MCHP_RESET_H_ */

include/zephyr/drivers/reset/mchp_rstc_g1.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file mchp_rstc_g1.h
+ * @brief Microchip RSTC G1 reset controller header
+ *
+ * This header includes the  Microchip RSTC G1 macro definitions.
+ */
+
+#ifndef INCLUDE_ZEPHYR_DRIVERS_RESET_MCHP_RSTC_G1_H_
+#define INCLUDE_ZEPHYR_DRIVERS_RESET_MCHP_RSTC_G1_H_
+
+/**
+ * @enum rstc_g1_rcause
+ * @brief Reset cause flags for Microchip RSTC G1.
+ *
+ * This enumeration defines the possible reset causes as indicated by the
+ * RSTC_RCAUSE register in the Microchip RSTC G1 reset controller.
+ */
+enum rstc_g1_rcause {
+	RSTC_G1_RCAUSE_POR = 0,   /* Power-on Reset */
+	RSTC_G1_RCAUSE_BOD12 = 1, /* Brown-Out 1.2V Detector Reset */
+	RSTC_G1_RCAUSE_BOD33 = 2, /* Brown-Out 3.3V Detector Reset */
+	RSTC_G1_RCAUSE_NVM = 3,   /* NVM Reset */
+	RSTC_G1_RCAUSE_EXT = 4,   /* External Reset */
+	RSTC_G1_RCAUSE_WDT = 5,   /* Watchdog Reset */
+	RSTC_G1_RCAUSE_SYST = 6,  /* System Reset Request */
+	RSTC_G1_RCAUSE_BACKUP = 7 /* Backup Reset */
+};
+
+#endif /* INCLUDE_ZEPHYR_DRIVERS_RESET_MCHP_RSTC_G1_H_ */