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stm32: tests: drivers : fix mpu faults by enabling SRAM clocks and configuring MPU regions on stm32h7rsx #97731

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stm32: tests: drivers : fix mpu faults by enabling SRAM clocks and configuring MPU regions on stm32h7rsx #97731

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5cd44f6
soc: st: stm32: stm32h7rsx: enable special_region to fix access viola…
djiatsaf-st Oct 16, 2025
b082bd1
drivers: clock_control: stm32: enable clocks for SRAM1 and SRAM2
djiatsaf-st Oct 16, 2025
8b9ef67
dts: arm: st: h7rs: Add zephyr,memory-attr to SRAM1 and SRAM2 regions
djiatsaf-st Oct 17, 2025
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8 changes: 8 additions & 0 deletions drivers/clock_control/clock_stm32_ll_h7.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1040,6 +1040,14 @@ int stm32_clock_control_init(const struct device *dev)
#endif
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);

#if defined(CONFIG_SOC_SERIES_STM32H7RSX)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sram1))
LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AHBSRAM1);
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sram2))
LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AHBSRAM2);
#endif
#endif
/* Set up individual enabled clocks */
set_up_fixed_clock_sources();

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2 changes: 2 additions & 0 deletions dts/arm/st/h7rs/stm32h7rs.dtsi
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Expand Up @@ -60,13 +60,15 @@
reg = <0x30000000 DT_SIZE_K(16)>;
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM1";
zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM)>;
};

/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
sram2: memory@30004000 {
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x30004000 DT_SIZE_K(16)>;
zephyr,memory-region = "SRAM2";
zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM)>;
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My PR #97364 most likely gets a problem with adding the memory attribute to sram2, because the order of MPU region initialization (see arm_mpu.c):

  1. elements from mpu_regions.c
  2. entries from the device tree with zephyr,memory-attr property
  3. entries resulting from CONFIG_USERSPACE, CONFIG_NOCACHE_MEMORY etc
  4. dynamic entries

As later defined regions overlapping earlier ones have a higher priority (called region overlay), the ATTR_MPU_RAM from dt will overlay the REGION_RAM_NOCACHE_ATTR / REGION_PPB_ATTR from my PR's mpu_regions.c. Never tried to overlay a smaller region with a bigger one, so maybe this is even illegal? Anyway, I need to figure a way to define my DMA memory regions after it is configured as standard memory.

I see the point of this change (and use it in my custom boards dts for other mem nodes), but how can I solve this?

};

dtcm: memory@20000000 {
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3 changes: 3 additions & 0 deletions soc/st/stm32/stm32h7rsx/mpu_regions.c
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Expand Up @@ -26,6 +26,9 @@ static const struct arm_mpu_region mpu_regions[] = {

/* Region 3 */
MPU_REGION_ENTRY("SRAM_0", CONFIG_SRAM_BASE_ADDRESS, REGION_RAM_ATTR(REGION_SRAM_SIZE)),

/* Special region */
MPU_REGION_ENTRY("SPECIAL_REGION", 0x08fff800, REGION_FLASH_ATTR(REGION_2K)),
};

const struct arm_mpu_config mpu_config = {
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