arch: riscv: custom: vexriscv: add cache driver #97925
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Add SpinalHDL vendor prefix. Signed-off-by: Fin Maaß <[email protected]>
zephyrbot
added
area: Boards/SoCs
area: Devicetree Bindings
area: Devicetree
area: RISCV
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edersondisouza,
fkokosinski,
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fkokosinski
reviewed
Oct 20, 2025
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| int arch_dcache_invd_all(void) | ||
| { | ||
| __asm__ volatile(".insn 0x500F\n"); |
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Nit: I'd maybe add a small comment here that this instruction is for invalidating the whole cache, and maybe this link: https://github.com/SpinalHDL/VexRiscv?tab=readme-ov-file#dbuscachedplugin
| "mv a0, %1\n" | ||
| "j 2f\n" | ||
| "3:\n" | ||
| ".insn 0x5500F\n" /* 0x500f | (a0 << 15) */ |
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ditto: add a comment about the address range we're invalidating here
add driver for VexRiscv CPU cache controller. Signed-off-by: Fin Maaß <[email protected]>
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add driver for VexRiscv CPU cache controller.
split from #93816