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arch: arm: mpu: move MPU memory configuration header #97934

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Merged
merged 17 commits into from
Oct 22, 2025
Merged

arch: arm: mpu: move MPU memory configuration header #97934

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db37097
arch: arm: mpu: move MPU memory configuration header
ibirnbaum Oct 20, 2025
818cd1e
arch: arm: core: mpu: adjust MPU header include
ibirnbaum Oct 20, 2025
d93d953
soc: xlnx: zynqmp: adjust MPU header include
ibirnbaum Oct 20, 2025
ed3f869
soc: ti: am6x: adjust MPU header include
ibirnbaum Oct 20, 2025
f86fd44
soc: st: stm32h7x: adjust MPU header include
ibirnbaum Oct 20, 2025
f4879c5
soc: renode: cortex_r8_virtual: adjust MPU header include
ibirnbaum Oct 20, 2025
d118aa6
soc: nxp: s32k3: adjust MPU header include
ibirnbaum Oct 20, 2025
2f8c81e
soc: nxp: imxrt: adjust MPU header include
ibirnbaum Oct 20, 2025
713c8dc
soc: nxp: imx8m: adjust MPU header include
ibirnbaum Oct 20, 2025
c152b37
soc: nuvoton: m55m1x: adjust MPU header include
ibirnbaum Oct 20, 2025
1e2777e
soc: nuvoton: npcx7: adjust MPU header include
ibirnbaum Oct 20, 2025
7302e7a
soc: nordic: nrf54hx: nrf92x: adjust MPU header include
ibirnbaum Oct 20, 2025
bb286c1
soc: infineon: cyq20829: adjust MPU header include
ibirnbaum Oct 20, 2025
76208a8
soc: adi: max32: adjust MPU header include
ibirnbaum Oct 20, 2025
7fda86e
boards: nxp: mimxrt1180_evk: adjust MPU header include
ibirnbaum Oct 20, 2025
6816ee9
soc: infineon: pse84: adjust MPU header include
ibirnbaum Oct 20, 2025
b362acf
soc: st: stm32h7rsx: adjust MPU header include
ibirnbaum Oct 20, 2025
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2 changes: 1 addition & 1 deletion arch/arm/core/mpu/arm_mpu_regions.c
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#include <zephyr/sys/slist.h>
#include <zephyr/arch/arm/mpu/arm_mpu.h>

#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>

static const struct arm_mpu_region mpu_regions[] = {
#ifdef CONFIG_XIP
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2 changes: 1 addition & 1 deletion boards/nxp/mimxrt1180_evk/cm7/mpu_regions.c
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*/

#include <zephyr/devicetree.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>

#define MEMORY_REGION_SIZE_KB(SIZE) (SIZE / 1024)

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6 changes: 3 additions & 3 deletions ...ephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h → ...ude/zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h
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*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ARM_CORTEX_M_MPU_MEM_CFG_H_
#define _ARM_CORTEX_M_MPU_MEM_CFG_H_
#ifndef _INCLUDE_ZEPHYR_ARCH_ARM_MPU_MEM_CFG_H_
#define _INCLUDE_ZEPHYR_ARCH_ARM_MPU_MEM_CFG_H_

#include <zephyr/arch/arm/mpu/arm_mpu.h>

Expand Down Expand Up @@ -119,4 +119,4 @@

#endif /* !ARMV8_M_BASELINE && !ARMV8_M_MAINLINE */

#endif /* _ARM_CORTEX_M_MPU_MEM_CFG_H_ */
#endif /* _INCLUDE_ZEPHYR_ARCH_ARM_MPU_MEM_CFG_H_ */
2 changes: 1 addition & 1 deletion soc/adi/max32/mpu_regions.c
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#include <zephyr/devicetree.h>
#include <zephyr/storage/flash_map.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>

/*
* Define noncacheable flash region attributes using noncacheable SRAM memory
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2 changes: 1 addition & 1 deletion soc/infineon/cat1b/cyw20829/mpu_regions.c
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*/

#include <zephyr/devicetree.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>

#define BOOTSTRAP_SAHB_RAM_BASE_ADDRESS DT_REG_ADDR(DT_NODELABEL(sram_bootstrap_sahb))
#define BOOTSTRAP_CBUS_RAM_BASE_ADDRESS DT_REG_ADDR(DT_NODELABEL(sram_bootstrap_cbus))
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2 changes: 1 addition & 1 deletion soc/infineon/edge/pse84/mpu_regions.c
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*/

#include <zephyr/devicetree.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>

/* We are expected to give *CONFIG_SIZE* in KB, but REGION_ATTR
* expects bytes, so we multiply by 1024 to convert.
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2 changes: 1 addition & 1 deletion soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c
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*/

#include <zephyr/devicetree.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>

#define USBHS_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(usbhs), core)
#define USBHS_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(usbhs), core)
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2 changes: 1 addition & 1 deletion soc/nuvoton/npcx/npcx7/mpu_regions.c
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* SPDX-License-Identifier: Apache-2.0
*/

#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>

static const struct arm_mpu_region mpu_regions[] = {
MPU_REGION_ENTRY("FLASH_0_0",
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2 changes: 1 addition & 1 deletion soc/nuvoton/numaker/m55m1x/mpu_regions.c
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*/

#include <zephyr/devicetree.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>

static const struct arm_mpu_region mpu_regions[] = {
MPU_REGION_ENTRY("FLASH",
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2 changes: 1 addition & 1 deletion soc/nxp/imx/imx8m/m7/mpu_regions.c
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*/

#include <zephyr/devicetree.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>

#define REGION_MASK_BASE_ADDRESS 0x00000000U
#define REGION_ITCM_BASE_ADDRESS 0x00000000U
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2 changes: 1 addition & 1 deletion soc/nxp/imxrt/mpu_regions.c
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#define SDRAM_BASE_ADDR 0x80000000

#include <zephyr/devicetree.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>

static const struct arm_mpu_region mpu_regions[] = {
/* Region 0 */
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2 changes: 1 addition & 1 deletion soc/nxp/s32/s32k3/mpu_regions.c
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#include <zephyr/devicetree.h>
#include <zephyr/linker/devicetree_regions.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>

#if !defined(CONFIG_XIP)
extern char _rom_attr[];
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2 changes: 1 addition & 1 deletion soc/renode/cortex_r8_virtual/arm_mpu_regions.c
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*/

#include <zephyr/kernel.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>

extern const uint32_t __rom_region_start;
extern const uint32_t __rom_region_mpu_size_bits;
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2 changes: 1 addition & 1 deletion soc/st/stm32/stm32h7rsx/mpu_regions.c
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#include <zephyr/sys/slist.h>
#include <zephyr/arch/arm/mpu/arm_mpu.h>

#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>

static const struct arm_mpu_region mpu_regions[] = {
/* Use first region to prevent speculative access in entire memory space */
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2 changes: 1 addition & 1 deletion soc/st/stm32/stm32h7x/mpu_regions.c
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*/

#include <zephyr/devicetree.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>

static const struct arm_mpu_region mpu_regions[] = {
MPU_REGION_ENTRY("FLASH", CONFIG_FLASH_BASE_ADDRESS,
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2 changes: 1 addition & 1 deletion soc/ti/k3/am6x/r5/arm_mpu_regions.c
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* SPDX-License-Identifier: Apache-2.0
*/

#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>
#include <zephyr/devicetree.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/arm/mpu/arm_mpu.h>
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2 changes: 1 addition & 1 deletion soc/xlnx/zynqmp/arm_mpu_regions.c
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*/

#include <zephyr/kernel.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#include <zephyr/arch/arm/mpu/arm_mpu_mem_cfg.h>

extern const uint32_t __rom_region_start;
extern const uint32_t __rom_region_mpu_size_bits;
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