arch: Added initial OpenRISC port #98160
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.balign is available in the or1k GNU assembler, therefore ALIGN and PERFOPT_ALIGN are both configured use it. Signed-off-by: Joel Holdsworth <[email protected]> FIX: balign
A common set of macros: GTEXT(), GDATA(), WTEXT() and WDATA() is defined for Arm, Arm66, MIPS, RISC-V, RX and Xtensa. This patch adds OpenRISC to this set. Signed-off-by: Joel Holdsworth <[email protected]>
Existing versions of GEN_ABSOLUTE_SYM and GEN_ABSOLUTE_SYM_KCONFIG are defined for all supported architectures. This patch adds a definition of the same kind used for MIPS, RISC-V and Xtensa. Signed-off-by: Joel Holdsworth <[email protected]>
The OpenRISC or1k-elf GCC compiler output format is named "elf32-or1k". This patch adds an OUTPUT_FORMAT linker macro for this platform. Signed-off-by: Joel Holdsworth <[email protected]>
Zephyr maps the start and end of the rodata section with variables using the __rodata_region_start and __rodata_region_end. This patch adopts this convention for the OpenRISC architecture. Signed-off-by: Joel Holdsworth <[email protected]>
This patch adds support for the OpenRISC 1000 (or1k) architecture: a MIPS-like open hardware ISA which was first introduced in 2000. The thread switching implementation uses the modern Zephyr thread "switch" architecture. Signed-off-by: Joel Holdsworth <[email protected]>
In OpenRISC 1000, the stack pointer is stored in the r1 register. This patch stores the offset of this value within in the thread structure into the thread info offsets. Signed-off-by: Joel Holdsworth <[email protected]>
The OpenRISC 1000 Tick Timer is tightly coupled to the or1k CPU core, and
is explicitly designed to facilitate task scheduling and high-resolution
timing.
The timer is documented in Chapter 14 of the OpenRISC 1000 Architecture
Manual:
https://openrisc.io/or1k.html#__RefHeading__504849_595890882
Signed-off-by: Joel Holdsworth <[email protected]>
The Qemu emulator executable for the OpenRISC 1000 (or1k) architecture is named qemu-or1k. This patch adds this information to the qemu architecture suffix list. Signed-off-by: Joel Holdsworth <[email protected]>
Qemu includes support for the OpenRISC 1000 CPU architecture. This patch adds a Zephyr SoC definition which enables usage of this feature. The SoC definition closely mirrors the Qemu MIPS Malta SoC definition. Signed-off-by: Joel Holdsworth <[email protected]>
Qemu includes support for the OpenRISC 1000 CPU architecture. This patch adds a Zephyr virtual board definition which enables usage of this feature. The board definition closely mirrors the Qemu MIPS Malta board definition. Signed-off-by: Joel Holdsworth <[email protected]>
The OpenRISC CPU architecture is signified by the CONFIG_OPENRISC Kconfig option. This patch adds this information to the log database ARCHS table. Signed-off-by: Joel Holdsworth <[email protected]>
Adds the openrisc CPU architecture to the twister platform definitions. Signed-off-by: Joel Holdsworth <[email protected]>
The OpenRISC 1000 architecture can be tested through the qemu_or1k emulated
SoC and board. Because this emulated device has minimal external hardware
by default, this patch enables a minimal suite of tests covering core
kernel features for the CPU architecture.
When running the test suite, OpenRISC was found to require additional stack
space to prevent an overflow. Therefore, a minimal additional amount of
storage: 128-bytes, was added that was found in practice to allow tests to
complete.
Note that Qemu version 9.2.0 or newer is required so as to include the
following commit:
commit 3eb43aeb164f1f83c97ff693c7d464b49755110c
Author: Joel Holdsworth <[email protected]>
Date: Fri Jun 7 15:29:33 2024 -0700
hw/openrisc: Fixed undercounting of TTCR in continuous mode
This fixes a bug in the implementation of the emulated OpenRISC Tick Timer
which prevents the Zephyr OpenRISC port from task-scheduling properly.
Signed-off-by: Joel Holdsworth <[email protected]>
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Can you explain why openrisc is a separate architecture to risc (I don't have knowledge on them but assumed they would be the ISA compatible?) |
henrikbrixandersen
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Architecture Review
You can refer to https://openrisc.io/ |
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| #if defined(CONFIG_SOC_PREP_HOOK) | ||
| soc_prep_hook(); | ||
| #endif |
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the if is not needed, it is already handled in zephyr/platform/hooks.h
did you meant RISCV? they are completely different, just like ARM and RISCV are |
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This PR follows on from #83933 which was closed due to inactivity. It has been many months since I have had any time to put into up-streaming these patches, so the PR was automatically closed.
Here is v9 of the patch-set with the following changes:
Interatively.z_openrisc_thread_startforSECTION_FUNC, because we don't want a section division here when_isr_tailfalls through to it.r0is initialized to zero (thanks @zgliu799).irq.hand make them inline.__resetand__startlabels into reset exception handler.z_check_stack_sentinelin_isr_tail. It is already called inz_get_next_switch_handle.z_check_stack_sentinelinz_openrisc_handle_irqs.r15in_isr_tail.load_caller_savedaferload_macandload_esr_epcrfor symmetry with storage macros.noloadandbsssections so as not to pad output image.include/zephyr/arch/openrisc/arch.hsimilar to matchinclude/zephyr/arch/mips/arch.h.The Zephyr port for the proprietary cousin of this architecture has now entered full production.
@zgliu799 has tested v8 version of the patches running an OpenRISC processor on an FPGA, and reports that they have worked successfully. He has also test the build using the Zephyr or1k tool-chain from the sdk-ng PR.
The sdk-ng patches are the main roadblock to getting this PR merged. They have been tested and rebased on the sdk-ng
mainbranch.