drivers: spi: siwx91x: SPI driver fixes to enable higher burst rates #99860
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smalae
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Nov 23, 2025
smalae
commented
- Setting INTF PLL to 160 MHz so GSPI has a stable, high-rate base clock, and QSPI gets the expected 80 MHz.
- Rounding the GSPI frequency down to a valid step derived from the INTF PLL (f = PLL/(2*div)), and logging the requested vs programmed rate.
- Enabling higher GPDMA burst sizes (1/2/4) when safe (SPI ≥ 10 MHz and both channels use GPDMA). The burst size is selected from the largest value that satisfies TX/RX buffer alignment, and FIFO thresholds are set accordingly. A temporary limitation notes DMA flow-control issues at low SPI rates, so bursts are gated behind the 10 MHz threshold.
- Fixing 16-bit transfers by swapping write/read data paths in the GSPI controller (GSPI_CONFIG2_b), ensuring the correct signal presentation on the SPI lines.
- Guarding async callback registration to avoid build errors when using blocking DMA transfers without CONFIG_SPI_ASYNC.
- Updating tests: increase CONFIG_SPI_IDEAL_TRANSFER_DURATION_SCALING from 24 → 26 to account for the (slightly) increased transfer time due to burst-size calculation.
- Enable the spi_loopback test for the PSRAM board siwx917_rb4342a.
- Add spi peripheral to the supported features of siwx917_rb4342a.
The GSPI and QSPI peripherals run on the interface PLL clock. To ensure correct operation, the interface PLL frequency should be set to 160 MHz. This provides a base clock of 80 MHz to the QSPI peripheral, which matches its required operating frequency. The GSPI peripheral can continue to operate at higher frequencies as it receives the full interface PLL clock. Signed-off-by: Sai Santhosh Malae <[email protected]>
smalae
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Add gspi_siwx91x_pick_lower_freq() to select the nearest lower supported GSPI clock frequency based on the requested value. The GSPI clock can operate only at discrete frequencies such as 80 MHz, 40 MHz, 26.6 MHz, 20 MHz, and so on (80 MHz divided by integer factors). If the requested frequency does not match one of these valid steps, it is rounded down to the nearest lower supported frequency. The driver now logs both the requested and the actual programmed frequency along with the divider value, helping users verify the effective SPI clock configuration. Signed-off-by: Sai Santhosh Malae <[email protected]>
Enable higher SPI burst sizes when using GPDMA to improve throughput. Bursts are only enabled when both TX and RX channels use GPDMA and the SPI clock frequency is at least 10 MHz, as DMA flow control is unreliable at lower SPI rates. Signed-off-by: Sai Santhosh Malae <[email protected]>
Swap the write and read data paths within the GSPI controller to ensure correct data is seen on the SPI lines during 16-bit transfers. Signed-off-by: Sai Santhosh Malae <[email protected]>
Guard callback registration with CONFIG_SPI_ASYNC to avoid build error for blocking SPI transfers using DMA Signed-off-by: Sai Santhosh Malae <[email protected]>
Increase CONFIG_SPI_IDEAL_TRANSFER_DURATION_SCALING to compensate for the additional burst size calculation in the SPI driver, which slightly increases transfer time. Signed-off-by: Sai Santhosh Malae <[email protected]>
Update testcase.yaml to enable the spi_loopback test for the siwx917_rb4342a board. Signed-off-by: Sai Santhosh Malae <[email protected]>
Add SPI to the supported list in siwx917_rb4342a.yaml to reflect hardware capability on the PSRAM-based SiWx917 Radio Board. Signed-off-by: Sai Santhosh Malae <[email protected]>
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