FPGA-accelarated-VSLAM

Python simulation

• Using the zip file of the repository:-https://github.com/rpautrat/SuperPoint
• For alike algorithm :- https://github.com/Shiaoming/ALIKE.git

Vitis HLS

• PROJECT NAME : alike_dsc11
• TOP FUNCTION : dsc_block11
• For Zybo board : xc7z010-clg400-1
• Source files:
  • dsc_block11.cpp
  • dsc_block11.h
• Testbench file:
  • testbench11.cpp
• PROJECT NAME: normal_conv_layer
• TOP FUNCTION: conv_layer
• Source files:
  • conv_layer.cpp
  • conv_layer.h
• Testbench file:
  • testbench_conv.cpp
• Vivado file name:
  • cnn_accelarator11
• Vivado std conv file name:
  • cnn_accelarator_stdconv