Shi Jin(Jason Shi), MS Candidate in CS. // Focusing: HPC | FPGA | Network // Active: 07:00 - 22:00 (UTC+8)
- Hangzhou, China
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09:52
(UTC +08:00)
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getting-started-guide-and-introduction-to-MXMACA
getting-started-guide-and-introduction-to-MXMACA PublicForked from bxttttt/getting-started-guide-and-introduction-to-MXMACA
C++
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taxi
taxi PublicForked from alexforencich/taxi
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
SystemVerilog
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