Systemverilog examples

Designs & synthesis scripts. This repository does not include libraries.

Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
ALU_64b		ALU_64b
addertree_128b		addertree_128b
axi @ f24b1fa		axi @ f24b1fa
comparator		comparator
light52 @ d4e4ee1		light52 @ d4e4ee1
lxp32-cpu @ 984250e		lxp32-cpu @ 984250e
lxp32-cpu-syn		lxp32-cpu-syn
systemverilog-tut		systemverilog-tut
test_clock_latency		test_clock_latency
test_dont_touch		test_dont_touch
verilog-axi @ 38915fb		verilog-axi @ 38915fb
wallace_hand_vs_auto		wallace_hand_vs_auto
.gitignore		.gitignore
.gitmodules		.gitmodules
Makefile		Makefile
README.md		README.md
dcrun.tcl		dcrun.tcl
example.sdc		example.sdc
fsm_seq1011_3alw.v		fsm_seq1011_3alw.v
interface_with_sv_design.sv		interface_with_sv_design.sv
interface_with_verilog_design.sv		interface_with_verilog_design.sv
modport.sv		modport.sv
serial24to128.v		serial24to128.v
top.sv		top.sv

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