All issues

Search results

Add GW1N-2 support

Status: Open.

#515 In YosysHQ/apicula;

· DavidClawson opened on Jun 13, 2026

GW2AR-18 (Tang Nano 20K): design with yosys-inferred ALU carry cells computes wrong on silicon; RTL sim, gate-level netlist sim, and timing all pass; synth_gowin -noalu fixes it

Status: Open.

#514 In YosysHQ/apicula;

· antonlebed opened on Jun 10, 2026

IOBUF ports swapped?

Status: Open.

#507 In YosysHQ/apicula;

· ric96 opened on May 25, 2026

find_sdram_pins.py doesn't work

Status: Open.

#506 In YosysHQ/apicula;

· lab313ru opened on May 23, 2026

Please harmonize the parameters of Gowin builds

Status: Open.

#482 In YosysHQ/apicula;

· zapta opened on Mar 16, 2026

Requesting Support for GW1N-UV1P5

Status: Open.

#436 In YosysHQ/apicula;

· Oichkatzelesfrettschen opened on Jan 24, 2026

Conflict bank VCC at IOL47A error when setting bank 6 to 3.3V.

Status: Open.

#433 In YosysHQ/apicula;

· zapta opened on Jan 21, 2026

GW5A-25 PLLA issue

Status: Open.

#427 In YosysHQ/apicula;

· Mandarancio opened on Dec 11, 2025

gowin_pack permits illegal values in rPLL ODIV_SEL

Status: Open.

#409 In YosysHQ/apicula;

· TheZoq2 opened on Oct 26, 2025

Detailed Circuit Diagrams

Status: Open.

#393 In YosysHQ/apicula;

· PythonLinks opened on Sep 29, 2025

Litex build with Apicula drops into PDB shell during routing state of gowin_pack.py, "<Src>,<Dst> not found in tile <row>, <col>"

Status: Open.

#354 In YosysHQ/apicula;

· Paumanok opened on Jul 4, 2025

Question about DSP, way to use it with pre-adders and cascading as single big block, and cascading those ?

Status: Open.

#353 In YosysHQ/apicula;

· Pe3ucTop opened on Jun 27, 2025