Olimex GateMateA1-EVB

This repository aims to provide a starting for projects with the Olimex GateMateA1-EVB board featuring a CologneChip GateMateA1 FPGA and a Raspberry RP2040 MCU.

Setup

The project is intended to be self contained based on devenv. The otherwise recommended tools can also be obtained via the OSS-CAD-Suite by YosysHQ.

Important

The current release of nextpnr does not support the GateMate FPGA. Therefore we have to rely on the daily builds. The toolchain can be obtained by executing the download_build_tools script provided by devenv! This will be installed automatically when you start your devenv shell.

Project Structure

This repo provides a basic folder structure which is explained now:

devenv.* files

These files provide the configuration for the development environment used to execute the toolchain. They are accompanied by some files like .envrc and .devevn.flake.nix.

Note

For more information please refer to the devenv user manual.

docs

The docs folder contains additional information, like the CologenChip GateMate A1 Manual.

external

The external directory contains files required to synthesize, generate, or flash the FPGA.

• config.mk -> root Makefile providing all necessary targets/tooling
• config_verilog.mk -> Makefile with Verilog specific file targets
• config_vhdl.mk -> Makefile with VHDL specific file targets
• dirtyJtag.uf2 -> RP2040 executable to use the RP2040 as a JTAG probe for flashing the FPGA

src

The src directory contains the actual Verilog/VHDL source files for the project.

out

The out directory contains the synthesis targets and generated bitstream files.

sim

The sim directory contains tesbenches and runtimes for simulation tasks

Makefile

The Makefile is the root for the make tool to build the project. You can use this one in order to define the HDL and the FPGA target.

Building Targets and Flashing the FPGA

1. Open the devenv shell.
2. Stay in the main project folder.
3. There are several ways to build the bitstream: i) all steps: make all, ii) only implementation and bitstream: make bitstream
4. Flash the FPGA
   1. Connect the FPGA to the PC
   2. Flash dirtyJTAG to the RP2040: flash_dirty_jtag
   3. Flash the bitstream file: make flash

Run Simulations

1. Go to the module directory: cd blink
2. Run the simulation and show the results: make wave