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Fix TCP stack – vFPGA routing and add TCP performance examples - #149

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adpp00 wants to merge 2 commits into
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adpp00:tcp
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Fix TCP stack – vFPGA routing and add TCP performance examples#149
adpp00 wants to merge 2 commits into
fpgasystems:masterfrom
adpp00:tcp

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@adpp00

@adpp00 adpp00 commented Oct 31, 2025

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Description

This pull request includes:

  1. Fix routing between the TCP stack and vFPGA
  2. Add new TCP examples (tcp_perf)

Type of change

  • Bug fix
  • New feature
  • Documentation update
  • A new research paper code implementation
  • Other

Tests & Results

Verified the fix and performance through the new tcp_perf example.
Results and detailed instructions are included in the README file /examples/11_perf_tcp/README.md.

  • Tested the data path between the TCP stack and vFPGA using tcp_perf
  • Achieved throughput up to 100 Gbps on hardware
  • No errors during synthesis or runtime

Checklist

  • I have commented my code and made corresponding changes to the documentation.
  • I have added tests/results that prove my fix is effective or that my feature works.
  • My changes generate no new warnings or errors & all tests successfully pass.

@bo3z bo3z added this to the 0.3.0 milestone Nov 8, 2025
@bo3z
bo3z self-requested a review November 21, 2025 02:24
@bo3z bo3z added the bugfix Fix for a bug label Nov 21, 2025

@bo3z bo3z left a comment

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Thank you for bringing back the TCP/IP stack. The code looks very good. I've finished the review and there are some minor comments that cover corner cases and make sure the TCP/IP stack follows the same design principles as other components in Coyote. I can look into addressing these.

Comment thread cmake/FindCoyoteHW.cmake
Comment thread hw/hdl/mmu/mmu_top.sv
Comment thread hw/hdl/shell/cnfg_slave.sv
Comment thread hw/hdl/shell/cnfg_slave_avx.sv
Comment thread hw/templates/user_wrapper_tmplt.txt
Comment thread hw/hdl/network/tcp/tcp_conn_table.sv
Comment thread hw/hdl/network/tcp/tcp_port_table.sv
Comment thread hw/hdl/network/tcp/tcp_rx_arbiter.sv
Comment thread hw/hdl/network/tcp/tcp_rx_arbiter.sv
logic [N_REGIONS-1 : 0] s_axis_tx_last;
logic [AXI_DATA_BITS-1 : 0] s_axis_tx_data [N_REGIONS];

for(genvar i = 0; i < N_REGIONS; i++) begin

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As above, we should check if these arrays will synthesize correctly in a genvar block.

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2 participants