Transmon qubit example with inductance port

[mdmaas]

This PR was made to enable modelling of a transmon qubit as an "inductance port".

Changes:

• Emit user resistance/inductance/capacitance as a port with active=false
• Keep LumpedPort R mapped from port.impedance only.

Debugging tools:

• Added a validate_mesh() function that checks if the lumped ports are rectangular, and if not, explains which one is failing.

[codecov]

Codecov Report

❌ Patch coverage is 71.91011% with 75 lines in your changes missing coverage. Please review.
✅ Project coverage is 55.18%. Comparing base (e9e4e48) to head (a86c3ec).
⚠️ Report is 92 commits behind head on main.

Files with missing lines	Patch %	Lines
src/gsim/palace/mesh/validation.py	69.09%	42 Missing and 26 partials ⚠️
src/gsim/palace/mesh/config_generator.py	82.75%	1 Missing and 4 partials ⚠️
src/gsim/palace/models/results.py	71.42%	1 Missing and 1 partial ⚠️

Additional details and impacted files

@@            Coverage Diff             @@
##             main     #110      +/-   ##
==========================================
+ Coverage   46.74%   55.18%   +8.43%     
==========================================
  Files          57       59       +2     
  Lines        6197     6756     +559     
  Branches     1079     1222     +143     
==========================================
+ Hits         2897     3728     +831     
+ Misses       3003     2658     -345     
- Partials      297      370      +73     

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[dot-cross]

As the description says: CPW lumped port geometry is distorted and non-rectangular.

Displacing the port to a non curvature section doesn't fix the error.

But increasing the mesh order priority of ports fix it. It seems that a tiny piece of the rectangle was outside the sapphire path, and was cut against the superconductor, which had higher priority.