Issue#1511: Added new rule for variable declaration asssignment operator position

docs/rule_groups/structure_rule_group.rst

@@ -188,6 +188,7 @@ Rules Enforcing Structure Rule Group
 * `variable_007 <../variable_rules.html#variable-007>`_
 * `variable_015 <../variable_rules.html#variable-015>`_
 * `variable_017 <../variable_rules.html#variable-017>`_
+* `variable_018 <../variable_rules.html#variable-018>`_
 * `variable_assignment_006 <../variable_assignment_rules.html#variable-assignment-006>`_
 * `variable_assignment_007 <../variable_assignment_rules.html#variable-assignment-007>`_
 * `variable_assignment_008 <../variable_assignment_rules.html#variable-assignment-008>`_

docs/variable_rules.rst

@@ -301,6 +301,31 @@ This rule checks the structure of variable constraints.
        element2(3 downto 0)
      );
 
+variable_018
+############
+
+|phase_1| |error| |structure|
+
+This rule checks the **:=** is on the same line as the **variable** keyword.
+
+**Violation**
+
+.. code-block:: vhdl
+
+   variable size : integer
+      := 1;
+   variable width : integer
+      := 32;
+
+**Fix**
+
+.. code-block:: vhdl
+
+   variable size    : integer :=
+     1;
+   variable width   : integer :=
+     32;
+
 variable_100
 ############
 

tests/variable/rule_018_test_input.fixed.vhd

@@ -0,0 +1,45 @@
+
+architecture RTL of FIFO is
+
+begin
+
+  my_proc : process
+
+    variable c_width : integer;
+
+    variable c_width : integer := 16;
+
+    variable c_depth : integer :=
+     512;
+
+    variable AVMM_MASTER_NULL  : avmm_master_t := (
+      (others => '0'),
+      (others => '0'),
+      '0',
+      '0'
+    );
+
+    --! Test stimulus
+      CONSTANT c_stimulus : t_stimulus_array :=
+      (
+          (
+              name      => "Hold in reset       ",
+              clk_in    => "0101010101010101",
+              rst_in    => "1111111111111111",
+              cnt_en_in => "0000000000000000",
+              cnt_out   => "0000000000000000"
+          ),
+          (
+              name      => "Not enabled         ",
+              clk_in    => "0101010101010101",
+              rst_in    => "0000000000000000",
+              cnt_en_in => "0000000000000000",
+              cnt_out   => "0000000000000000"
+          )
+    );
+
+  begin
+
+  end process;
+
+end architecture RTL;

tests/variable/rule_018_test_input.vhd

@@ -0,0 +1,45 @@
+
+architecture RTL of FIFO is
+
+begin
+
+  my_proc : process
+
+    variable c_width : integer;
+
+    variable c_width : integer := 16;
+
+    variable c_depth : integer
+    := 512;
+
+    variable AVMM_MASTER_NULL  : avmm_master_t := (
+      (others => '0'),
+      (others => '0'),
+      '0',
+      '0'
+    );
+
+    --! Test stimulus
+      CONSTANT c_stimulus : t_stimulus_array :=
+      (
+          (
+              name      => "Hold in reset       ",
+              clk_in    => "0101010101010101",
+              rst_in    => "1111111111111111",
+              cnt_en_in => "0000000000000000",
+              cnt_out   => "0000000000000000"
+          ),
+          (
+              name      => "Not enabled         ",
+              clk_in    => "0101010101010101",
+              rst_in    => "0000000000000000",
+              cnt_en_in => "0000000000000000",
+              cnt_out   => "0000000000000000"
+          )
+    );
+
+  begin
+
+  end process;
+
+end architecture RTL;

tests/variable/test_rule_018.py

@@ -0,0 +1,46 @@
+# -*- coding: utf-8 -*-
+
+import os
+import unittest
+
+from tests import utils
+from vsg import vhdlFile
+from vsg.rules import variable
+
+sTestDir = os.path.dirname(__file__)
+
+lFile, eError = vhdlFile.utils.read_vhdlfile(os.path.join(sTestDir, "rule_018_test_input.vhd"))
+
+lExpected = []
+lExpected.append("")
+utils.read_file(os.path.join(sTestDir, "rule_018_test_input.fixed.vhd"), lExpected)
+
+
+class test_rule(unittest.TestCase):
+    def setUp(self):
+        self.oFile = vhdlFile.vhdlFile(lFile)
+        self.assertIsNone(eError)
+
+    def test_rule_018(self):
+        oRule = variable.rule_018()
+        self.assertTrue(oRule)
+        self.assertEqual(oRule.name, "variable")
+        self.assertEqual(oRule.identifier, "018")
+        self.assertEqual(oRule.groups, ["structure"])
+
+        lExpected = [12]
+
+        oRule.analyze(self.oFile)
+        self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
+
+    def test_fix_rule_018(self):
+        oRule = variable.rule_018()
+
+        oRule.fix(self.oFile)
+
+        lActual = self.oFile.get_lines()
+
+        self.assertEqual(lExpected, lActual)
+
+        oRule.analyze(self.oFile)
+        self.assertEqual(oRule.violations, [])

vsg/rules/variable/__init__.py

@@ -12,6 +12,7 @@
 from .rule_012 import rule_012
 from .rule_015 import rule_015
 from .rule_017 import rule_017
+from .rule_018 import rule_018
 from .rule_100 import rule_100
 from .rule_101 import rule_101
 from .rule_102 import rule_102

vsg/rules/variable/rule_018.py

@@ -0,0 +1,36 @@
+# -*- coding: utf-8 -*-
+
+from vsg import token
+from vsg.rules import move_token_left_to_next_non_whitespace_token as Rule
+
+lTokens = []
+lTokens.append(token.variable_declaration.assignment_operator)
+
+
+class rule_018(Rule):
+    """
+    This rule checks the **:=** is on the same line as the **variable** keyword.
+
+    **Violation**
+
+    .. code-block:: vhdl
+
+       variable size : integer
+          := 1;
+       variable width : integer
+          := 32;
+
+    **Fix**
+
+    .. code-block:: vhdl
+
+       variable size    : integer :=
+         1;
+       variable width   : integer :=
+         32;
+    """
+
+    def __init__(self):
+        super().__init__(lTokens)
+        self.bRemoveTrailingWhitespace = False
+        self.solution = "Move := operator"