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Pull requests: llvm/circt

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Pull requests list

[MooreToCore][Sim] Support lowering of unpacked array equality
#10835 opened Jul 16, 2026 by VecoMr Member Loading…
1
Dev/jpk/issue 8390
#10834 opened Jul 16, 2026 by jpkirs • Draft
1
[RTG] Add algebraic effect system (mut cells, handlers, continuations) RTG Involving the `rtg` dialect
#10828 opened Jul 14, 2026 by youngar Member Loading…
1
[Probe] Add read-only probe dialect and HW port restrictions
#10818 opened Jul 11, 2026 by nanjo712 Contributor Loading…
5
[MooreToCore] Support moore.concat_ref lowering
#10816 opened Jul 11, 2026 by VecoMr Member Loading…
2
[Synth] Plumb input caps into TechMapper
#10813 opened Jul 10, 2026 by okekayode Contributor Loading…
1
[OM] Handle signless OM integers in folding
#10812 opened Jul 10, 2026 by uenoku Member Loading…
1
3
[Moore] SimplifyRefs: lower concat_ref destinations of delayed assignments
#10808 opened Jul 9, 2026 by AmurG Contributor Loading…
1
[MooreToCore] Fold case equality against x/z-bearing constants to its static verdict
#10807 opened Jul 9, 2026 by AmurG Contributor Loading…
1
[FIRRTL] Add RWProbe force/release synthesis to ProbesToSignals
#10803 opened Jul 9, 2026 by prithayan Contributor Loading…
3
[ImportVerilog] Look through labels on module-level concurrent assertions
#10796 opened Jul 8, 2026 by AmurG Contributor Loading…
1
[Sim][Moore] Make zero-operand queue.concat round-trippable
#10795 opened Jul 8, 2026 by AmurG Contributor Loading…
1
[LLHD] Add llhd.resample: pin event-trigger samples to their check block
#10794 opened Jul 8, 2026 by AmurG Contributor Loading…
4
[LLHD] Deseq: handle signals with multiple drivers soundly
#10793 opened Jul 8, 2026 by AmurG Contributor Loading…
1
[ExportVerilog] Legalize EnumFieldAttr types in anonymous enum pass
#10791 opened Jul 8, 2026 by ConvolutedDog Contributor Loading…
2
[Calyx] Avoid invalid intermediate IR in common-tail canonicalization
#10790 opened Jul 8, 2026 by skku970412 Loading…
1
[VerifToSMT] Keep assumptions asserted across BMC timesteps
#10788 opened Jul 7, 2026 by leizaf Contributor • Draft
1
[FIRRTL][InferDomains] Add option to skip checking specific domains
#10763 opened Jul 2, 2026 by uenoku Member • Draft
1
Bump LLVM
#10756 opened Jul 2, 2026 by uenoku Member Loading…
3
[FSM] Eliminate mutually exclusive transition guards (#3577)
#10754 opened Jul 1, 2026 by arefinaa Loading…
2 tasks done
1
[circt-bmc] Add verif.bmc.trace for BMC counterexample value tracking
#10747 opened Jul 1, 2026 by 5iri Contributor Loading…
8
[ImportVerilog][MooreToCore] Adds support for System Verilog real maths functions
#10746 opened Jun 30, 2026 by jpkirs Loading…
3
[Python] Fix ModuleLike.is_external for ops with no region
#10745 opened Jun 30, 2026 by uenoku Member Loading…
1
[FIRRTL] Add edge attribute to LTL clock intrinsic
#10744 opened Jun 29, 2026 by Clo91eaf Contributor Loading…
2
Adding support for the Verilog Real Math system as non synthesisable constructs
#10743 opened Jun 29, 2026 by jpkirs • Draft
ProTip! Updated in the last three days: updated:>2026-07-13.