🖥️ RISC-V Assembly Lab — Performance Analysis

RISC-V assembly programs and performance analysis reports for the Computer Organization & Architecture (COA) course (PBCST404).
Each experiment includes the assembly source (.s), assembled binary (.bin), equivalent C program, a detailed report, and Ripes simulator screenshots.

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👥 Group 5

Ahammed Halim · Anakha Shaju · Aravind Lal · Madhav S

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📂 Experiments

📦 Array Maximum & Minimum

Finds the maximum and minimum values in an integer array. Includes performance comparison between Single Cycle and 5-Stage Pipelined RISC-V processors.

File	Description
Array-max-min.s	RISC-V assembly source
Array-max-min.bin	Assembled binary
array_max_min.c	Equivalent C program
README.md	Full performance analysis report with screenshots

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🛠️ Tools Used

Tool	Purpose
Ripes	RISC-V assembler, simulator & pipeline visualizer — used to write, assemble, execute, and analyze all programs
Git	Version control

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🚀 Getting Started with Ripes

1. Download and install Ripes
2. Open Ripes → Editor tab
3. Load or paste any .s file from this repo
4. Click Assemble
5. Use the Processor tab to step through execution and inspect registers & memory
6. Switch between Single Cycle and 5-Stage Pipelined processors to compare performance

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📄 License

This repository is for academic/educational purposes only as part of university COA lab coursework.