Open hardware/software research for NPU architecture, FPGA acceleration, and AI-assisted verification.
Specification, documentation, and release coordination across the ecosystem.
RTL, Sail reference, and KV260 bring-up artifacts. Hardware evidence lives here.
CLI-first verification lab. Provides the shared analyze and status boundary that editor and launcher integrations consume. Plugin system and MCP interface are planned. GUI is a secondary surface.
SystemVerilog IDE spin-out from pccx-lab. Targets diagnostics, xsim log integration, and an AI-assisted SystemVerilog development workflow.
User-facing local LLM launcher, targeting KV260-class edge devices. Currently a planning scaffold; real launch flow depends on FPGA bring-up evidence from pccx-FPGA-NPU-LLM-kv260.
Execution is tracked on the PCCX Roadmap project. The short release-track summary lives at pccx/docs/roadmap.
Focused issues, documentation improvements, reproducible benchmarks, and small experiments are welcome.
See each repository's CONTRIBUTING.md for project-specific guidance.
Open a discussion before starting non-trivial work.
For security disclosures, see SECURITY.md. For other questions, file an issue in the relevant repository.
