Fixes for reloc overflows#1427
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Check for relocation overflows for R_AARCH64_ADR_PREL_PG_HI21 Add test that verifies a link within range succeeds and a link that overflows the 21-bit field is caught with an overflow diagnostic. Fixes #1329 Signed-off-by: Shankar Easwaran <seaswara@qti.qualcomm.com>
The ADR instruction encodes (S + A) - P in a 21-bit signed immediate field. Add a signed 21-bit range check for R_AARCH64_ADR_PREL_LO21. The LDR (literal) instruction encodes (S + A) - P in a 19-bit signed field scaled by 4. Add a signed 21-bit range check on the raw byte offset for R_AARCH64_LD_PREL_LO19. Since the field is scaled by 4, X must also be a multiple of 4 per ABI requirements; add a new error_reloc_not_aligned error diagnostic and return BadReloc if not. Add lit tests that verify a link within range succeeds, a link that overflows the 21-bit field is caught with an overflow diagnostic, and an R_AARCH64_LD_PREL_LO19 relocation with a misaligned X is caught with an alignment error. Update the AArch64 relocation developer documentation to record the 4-byte alignment requirement for LD_PREL_LO19. Signed-off-by: Shankar Easwaran <seaswara@qti.qualcomm.com>
…ARCH64_JUMP26 BL/B encodes (S + A) - P in a 26-bit signed field scaled by 4 (+/-128MB). Unlike ADR/LDR, out-of-range branches are handled transparently via trampoline stub insertion rather than an overflow error. However, the PC-relative offset must still be 4-byte aligned; a misaligned target is always an input error. Add an alignment check (X & 0x3) in the call() relocator, matching the pattern already used by ld_prel_lo19. Expand the lit test to cover in-range, out-of-range (trampoline), and misaligned target cases. Signed-off-by: Shankar Easwaran <seaswara@qti.qualcomm.com>
Shankar Easwaran (quic-seaswara)
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Ana Pazos (apazos) and
Eli Friedman (efriedma-quic)
Eli Friedman (efriedma-quic)
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Jul 8, 2026
Eli Friedman (efriedma-quic)
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LGTM, assuming this is the same as the patch to main.
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