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debug genet issues #7378

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84e040b
net: bcmgenet: fix off-by-one in bcmgenet_put_txcb
Ryceancurry Apr 6, 2026
9608f18
net: bcmgenet: fix leaking free_bds
Ryceancurry Apr 6, 2026
11eec3c
net: bcmgenet: fix racing timeout handler
Ryceancurry Apr 6, 2026
d126e15
debug rbuf_/tbuf_pm
nbuchwitz May 19, 2026
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63 changes: 42 additions & 21 deletions drivers/net/ethernet/broadcom/genet/bcmgenet.c
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Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,26 @@
/* Forward declarations */
static void bcmgenet_set_rx_mode(struct net_device *dev);

/*
* Diagnostic knob for isolating GENET EEE/LPI failures.

Check failure on line 70 in drivers/net/ethernet/broadcom/genet/bcmgenet.c

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GitHub Actions / checkpatch review 

WARNING: networking block comments don't use an empty /* line, use /* Comment...
*
* Bit 0: UMAC EEE protocol handling
* Bit 1: TBUF EEE/power-management
* Bit 2: RBUF EEE/power-management
*
*/
#define GENET_EEE_PM_UMAC BIT(0)
#define GENET_EEE_PM_TBUF BIT(1)
#define GENET_EEE_PM_RBUF BIT(2)
#define GENET_EEE_PM_ALL (GENET_EEE_PM_UMAC | \
GENET_EEE_PM_TBUF | \
GENET_EEE_PM_RBUF)

static uint eee_pm_mask = GENET_EEE_PM_ALL;
module_param(eee_pm_mask, uint, 0444);
MODULE_PARM_DESC(eee_pm_mask,
"EEE power-management mask: bit0=UMAC bit1=TBUF bit2=RBUF");

static inline void bcmgenet_writel(u32 value, void __iomem *offset)
{
/* MIPS chips strapped for BE will automagically configure the
Expand Down Expand Up @@ -1347,37 +1367,40 @@
{
struct bcmgenet_priv *priv = netdev_priv(dev);
u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
u32 mask = enable ? eee_pm_mask : 0;
u32 reg;

if (enable && !priv->clk_eee_enabled) {
netdev_info_once(dev, "GENET EEE PM mask: 0x%x\n", eee_pm_mask);

if (mask && !priv->clk_eee_enabled) {
clk_prepare_enable(priv->clk_eee);
priv->clk_eee_enabled = true;
}

reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
if (enable)
if (mask & GENET_EEE_PM_UMAC)
reg |= EEE_EN;
else
reg &= ~EEE_EN;
bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);

/* Enable EEE and switch to a 27Mhz clock automatically */
reg = bcmgenet_readl(priv->base + off);
if (enable)
if (mask & GENET_EEE_PM_TBUF)
reg |= TBUF_EEE_EN | TBUF_PM_EN;
else
reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
bcmgenet_writel(reg, priv->base + off);

/* Do the same for thing for RBUF */
reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
if (enable)
if (mask & GENET_EEE_PM_RBUF)
reg |= RBUF_EEE_EN | RBUF_PM_EN;
else
reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);

if (!enable && priv->clk_eee_enabled) {
if (!mask && priv->clk_eee_enabled) {
clk_disable_unprepare(priv->clk_eee);
priv->clk_eee_enabled = false;
}
Expand Down Expand Up @@ -1815,15 +1838,15 @@
{
struct enet_cb *tx_cb_ptr;

tx_cb_ptr = ring->cbs;
tx_cb_ptr += ring->write_ptr - ring->cb_ptr;

/* Rewinding local write pointer */
if (ring->write_ptr == ring->cb_ptr)
ring->write_ptr = ring->end_ptr;
else
ring->write_ptr--;

tx_cb_ptr = ring->cbs;
tx_cb_ptr += ring->write_ptr - ring->cb_ptr;

return tx_cb_ptr;
}

Expand Down Expand Up @@ -1981,6 +2004,7 @@
drop = (ring->prod_index - ring->c_index) & DMA_C_INDEX_MASK;
released += drop;
ring->prod_index = ring->c_index & DMA_C_INDEX_MASK;
ring->free_bds += drop;
while (drop--) {
cb_ptr = bcmgenet_put_txcb(priv, ring);
skb = cb_ptr->skb;
Expand All @@ -1992,6 +2016,7 @@
}
if (skb)
dev_consume_skb_any(skb);
netdev_tx_reset_queue(netdev_get_tx_queue(dev, ring->index));
bcmgenet_tdma_ring_writel(priv, ring->index,
ring->prod_index, TDMA_PROD_INDEX);
wr_ptr = ring->write_ptr * WORDS_PER_BD(priv);
Expand Down Expand Up @@ -3473,27 +3498,23 @@
static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue)
{
struct bcmgenet_priv *priv = netdev_priv(dev);
u32 int1_enable = 0;
unsigned int q;
struct bcmgenet_tx_ring *ring = &priv->tx_rings[txqueue];
struct netdev_queue *txq = netdev_get_tx_queue(dev, txqueue);

netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");

for (q = 0; q <= priv->hw_params->tx_queues; q++)
bcmgenet_dump_tx_queue(&priv->tx_rings[q]);

bcmgenet_tx_reclaim_all(dev);
bcmgenet_dump_tx_queue(ring);

for (q = 0; q <= priv->hw_params->tx_queues; q++)
int1_enable |= (1 << q);
bcmgenet_tx_reclaim(dev, ring, true);

/* Re-enable TX interrupts if disabled */
bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
/* Re-enable the TX interrupt for this ring */
bcmgenet_intrl2_1_writel(priv, 1 << txqueue, INTRL2_CPU_MASK_CLEAR);

netif_trans_update(dev);
txq_trans_cond_update(txq);

BCMGENET_STATS64_INC((&priv->tx_rings[txqueue].stats64), errors);
BCMGENET_STATS64_INC((&ring->stats64), errors);

netif_tx_wake_all_queues(dev);
netif_tx_wake_queue(txq);
}

#define MAX_MDF_FILTER 17
Expand Down
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