mb/system76/ptl: Add Adder Pro 6 (addp6)

src/mainboard/system76/ptl/Kconfig

@@ -26,6 +26,12 @@ config BOARD_SYSTEM76_PTL_COMMON
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 
+config BOARD_SYSTEM76_ADDP6
+	select BOARD_SYSTEM76_PTL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select EC_SYSTEM76_EC_DGPU
+	select EC_SYSTEM76_EC_OLED
+
 config BOARD_SYSTEM76_LEMP14
 	select BOARD_SYSTEM76_PTL_COMMON
 	select DRIVERS_I2C_TAS5825M
@@ -46,19 +52,23 @@ config MAINBOARD_DIR
 	default "system76/ptl"
 
 config VARIANT_DIR
+	default "addp6" if BOARD_SYSTEM76_ADDP6
 	default "lemp14" if BOARD_SYSTEM76_LEMP14 || BOARD_SYSTEM76_LEMP14_B
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
 config MAINBOARD_PART_NUMBER
+	default "addp6" if BOARD_SYSTEM76_ADDP6
 	default "lemp14" if BOARD_SYSTEM76_LEMP14
 	default "lemp14-b" if BOARD_SYSTEM76_LEMP14_B
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Adder Pro" if BOARD_SYSTEM76_ADDP6
 	default "Lemur Pro" if BOARD_SYSTEM76_LEMP14 || BOARD_SYSTEM76_LEMP14_B
 
 config MAINBOARD_VERSION
+	default "addp6" if BOARD_SYSTEM76_ADDP6
 	default "lemp14" if BOARD_SYSTEM76_LEMP14
 	default "lemp14-b" if BOARD_SYSTEM76_LEMP14_B
 

src/mainboard/system76/ptl/Kconfig.name

@@ -1,5 +1,8 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+config BOARD_SYSTEM76_ADDP6
+	bool "addp6"
+
 config BOARD_SYSTEM76_LEMP14
 	bool "lemp14"
 

src/mainboard/system76/ptl/acpi/mainboard.asl

@@ -7,6 +7,9 @@
 Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
+#if !CONFIG(EC_SYSTEM76_EC_OLED)
 		#include "backlight.asl"
+#endif
+		/* TODO: Add NVIDIA include */
 	}
 }

src/mainboard/system76/ptl/variants/addp6/board.fmd

@@ -0,0 +1,12 @@
+FLASH 32M {
+	SI_DESC 16K
+	SI_ME 9176K
+	SI_BIOS@16M 16M {
+		RW_MRC_CACHE 64K
+		SMMSTORE(PRESERVE) 512K
+		WP_RO {
+			FMAP 4K
+			COREBOOT(CBFS)
+		}
+	}
+}

src/mainboard/system76/ptl/variants/addp6/board_info.txt

@@ -0,0 +1,2 @@
+Board name: addp6
+Release year: 2026

src/mainboard/system76/ptl/variants/addp6/gpio.c

@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET#
+
+	PAD_NC(GPP_A08, NONE), // SOC_SML_SCL (NC)
+	PAD_NC(GPP_A09, NONE), // SOC_SML_SDA (NC)
+	PAD_NC(GPP_A10, NONE),
+	PAD_CFG_GPO(GPP_A11, 1, DEEP), // WLAN_RST#
+	PAD_NC(GPP_A12, NONE), // WLAN_WAKEUP# (NC)
+	PAD_NC(GPP_A13, NONE), // NVVDD_TALERT# (NC?)
+	PAD_NC(GPP_A15, NONE), // EPD_ON_GCD_IN
+	PAD_NC(GPP_A16, NONE), // PCH_BT_EN (NC)
+	PAD_CFG_GPO(GPP_A17, 1, NONE), // WIFI_RF_EN
+
+	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), // SOC_SMLINK_I2C_SCL
+	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), // SOC_SMLINK_I2C_SDA
+	PAD_NC(GPP_B02, NONE),
+	PAD_NC(GPP_B03, NONE),
+	PAD_CFG_GPI(GPP_B04, NONE), // CPU_ME_WE / Flash Descriptor Security Override strap
+	PAD_NC(GPP_B05, NONE), // PS8461_SW_PCH (NC)
+	PAD_NC(GPP_B06, NONE),
+	PAD_NC(GPP_B07, NONE),
+	PAD_NC(GPP_B08, NONE),
+	//PAD_NC(GPP_B09, NONE), // M2_SSD2_RST#
+	PAD_NC(GPP_B10, NONE), // CPU_HDMI_HPD (NC?)
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), // TCP2_HPD (CPU_TYPEC1_DP_HPD)
+	PAD_NC(GPP_B12, NONE), // SLP_S0# (NC)
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), // TCP3_HPD (CPU_TYPEC2_DP_HPD)
+	PAD_CFG_GPI(GPP_B15, NONE), // USB_OC3# (10k P/U to 1.8VA)
+	//PAD_NC(GPP_B16, NONE), // SSD1_PWR_EN
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B18, NONE),
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_NC(GPP_B22, NONE),
+	PAD_NC(GPP_B23, NONE), // Reserved strap
+	PAD_NC(GPP_B24, NONE),
+	PAD_NC(GPP_B25, NONE),
+
+	PAD_NC(GPP_C00, NONE), // SMB_CLK_DDR (NC)
+	PAD_NC(GPP_C01, NONE), // SMB_DATA_DDR (NC)
+	PAD_NC(GPP_C02, NONE), // TLS confidentiality strap
+	PAD_NC(GPP_C03, NONE), // SOC_LAN_SML0_SCL (NC)
+	PAD_NC(GPP_C04, NONE), // SOC_LAN_SML0_SDA (NC)
+	PAD_NC(GPP_C05, NONE), // eSPI disable strap
+	PAD_NC(GPP_C06, NONE), // SOC_SML1_SCL (NC)
+	PAD_NC(GPP_C07, NONE), // SOC_SML1_SDA (NC)
+	PAD_NC(GPP_C08, NONE),
+	PAD_NC(GPP_C09, NONE),
+	PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), // GPU_CLK1REQ#_N
+	PAD_NC(GPP_C11, NONE),
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), // LAN_CLK3REQ#_N
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), // WLAN_CLK4REQ#_N
+	//PAD_NC(GPP_C14, NONE), // SSD1_CLK5REQ#_N
+	PAD_NC(GPP_C15, NONE), // Reserved strap
+	PAD_NC(GPP_C16, NONE),
+	PAD_NC(GPP_C17, NONE),
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+
+	PAD_CFG_GPO(GPP_D00, 1, DEEP), // SB_BLON
+	PAD_NC(GPP_D01, NONE), // FW_EN_PD (NC)
+	PAD_NC(GPP_D02, NONE), // FW_EN_RETIMER (NC)
+	PAD_NC(GPP_D03, NONE), // EC_SYS_PWROK (NC)
+	PAD_NC(GPP_D04, NONE),
+	PAD_NC(GPP_D05, NONE),
+	PAD_NC(GPP_D06, NONE),
+	PAD_NC(GPP_D07, NONE),
+	PAD_NC(GPP_D08, NONE),
+	//PAD_NC(GPP_D09, NONE), // DGPU_RST#
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), // HDA_SDOUT
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), // HDA_SDIN0
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE), // CNVI_WAKE#
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), // HDA_RST#
+	PAD_NC(GPP_D17, NONE),
+	//PAD_NC(GPP_D18, NONE), // SSD2_CLK6REQ#_N
+	PAD_CFG_GPI(GPP_D19, NONE, PLTRST), // 10k P/U to 1.8VS
+	PAD_NC(GPP_D20, NONE),
+	PAD_NC(GPP_D21, NONE),
+	PAD_CFG_GPI(GPP_D22, NONE, PLTRST), // 1k P/U to 1.8VA
+	PAD_CFG_GPI(GPP_D23, NONE, PLTRST), // 1k P/U to 1.8VA
+	PAD_NC(GPP_D24, NONE),
+	PAD_NC(GPP_D25, NONE),
+
+	PAD_CFG_GPI_SCI_LOW(GPP_E01, NONE, DEEP, EDGE_SINGLE), // TPM_PIRQ#
+	PAD_NC(GPP_E02, NONE), // VRALERT# (NC)
+	//PAD_NC(GPP_E03, NONE), // M2_SSD1_RST#
+	PAD_NC(GPP_E05, NONE),
+	PAD_NC(GPP_E06, NONE), // JTAG ODT strap
+	PAD_NC(GPP_E07, NONE),
+	//PAD_NC(GPP_E08, NONE), // SSD2_PWR_EN
+	PAD_CFG_GPI(GPP_E09, NONE), // USB_OC0# (10k P/U to 1.8VA)
+	PAD_NC(GPP_E10, NONE), // "QUALIFIED BY DFXTESTMODE" strap
+	//PAD_NC(GPP_E11, NONE), // BOARD_ID1
+	PAD_NC(GPP_E12, NONE),
+	PAD_NC(GPP_E13, NONE),
+	//PAD_NC(GPP_E14, NONE), // BOARD_ID2
+	//PAD_NC(GPP_E15, NONE), // BOARD_ID3
+	PAD_NC(GPP_E16, NONE),
+	//PAD_NC(GPP_E17, NONE), // BOARD_ID4
+	PAD_NC(GPP_E18, NONE),
+	PAD_NC(GPP_E19, NONE), // PCH_GPIO_LANRTD3 (NC)
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE), // SOC_SMLINK_I2C_INT (NC)
+	PAD_NC(GPP_E22, NONE),
+
+	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F01, NONE, UP_20K, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), // CNVI_RGI_DT / M.2 CNVi mode strap
+	PAD_CFG_NF(GPP_F03, NONE, UP_20K, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), // CNVI_RST#
+	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), // CNVI_CLKREQ
+	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F07, NONE),
+	PAD_NC(GPP_F08, NONE),
+	PAD_CFG_GPI(GPP_F09, NONE, PLTRST), // TPM_DET: 0=None, 1=Present
+	PAD_NC(GPP_F10, NONE),
+	PAD_NC(GPP_F11, NONE),
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), // I2C_SCL_TP
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), // I2C_SDA_TP
+	//PAD_NC(GPP_F14, NONE), // DGPU_PWR_EN
+	PAD_CFG_GPI(GPP_F15, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN (10k P/U to 1V8_AON)
+	PAD_CFG_GPO(GPP_F16, 0, DEEP), // CCD_WP#
+	PAD_CFG_GPI(GPP_F17, NONE), // GC6_FB_EN_PCH
+	PAD_CFG_GPI_APIC_LOW(GPP_F18, NONE, DEEP), // TP_ATTN#
+	PAD_NC(GPP_F19, NONE), // Reserved strap
+	//PAD_NC(GPP_F20, NONE), // DGPU_PWRGD
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	PAD_NC(GPP_H00, NONE), // eSPI Flash Sharing Mode strap: 0=CAFS, 1=TAFS
+	PAD_NC(GPP_H01, NONE), // Flash Descriptor Recovery strap
+	PAD_NC(GPP_H02, NONE), // Reserved strap
+	PAD_NC(GPP_H03, NONE),
+	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), // CPU_PD_I2C_SDA
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), // CPU_PD_I2C_SCL
+	//PAD_NC(GPP_H08, NONE), // UART_RX
+	//PAD_NC(GPP_H09, NONE), // UART_TX
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	PAD_NC(GPP_H13, NONE), // CPU_C10_GATE# (NC)
+	PAD_NC(GPP_H14, NONE),
+	PAD_NC(GPP_H15, NONE),
+	PAD_NC(GPP_H16, NONE),
+	PAD_NC(GPP_H17, NONE),
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE), // CPU_REDRIVER_I2C_SDA (NC)
+	PAD_NC(GPP_H22, NONE), // CPU_REDRIVER_I2C_SCL (NC)
+
+	PAD_NC(GPP_S00, NONE),
+	PAD_NC(GPP_S01, NONE),
+	PAD_NC(GPP_S02, NONE),
+	PAD_NC(GPP_S03, NONE),
+	PAD_NC(GPP_S04, NONE), // M.2_BT_PCMCLK (NC)
+	PAD_NC(GPP_S05, NONE), // M.2_BT_PCMFRM_CRF_RST_N (NC)
+	PAD_NC(GPP_S06, NONE), // M.2_BT_PCMOUT_CLKREQ0 (NC)
+	PAD_NC(GPP_S07, NONE), // M.2_BT_PCMIN (NC)
+
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // SOC_AC_PRESENT
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // PCH_LAN_WAKE# (NC?)
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // SOC_PWR_BTN#
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), // SLP_A# (NC?)
+	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), // SUS_CLK
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), // SLP_WLAN# (NC?)
+	PAD_NC(GPP_V09, NONE),
+	PAD_NC(GPP_V10, NONE),
+	PAD_NC(GPP_V11, NONE),
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), // PCH_WAKEUP#
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), // VCCST_EN
+	PAD_NC(GPP_V17, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+static const struct pad_config nvme_pwr_seq2[] = {
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST), // SSD1_PWR_EN
+	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), // SSD1_CLK5REQ#_N
+	PAD_CFG_GPO(GPP_E08, 1, PLTRST), // SSD2_PWR_EN
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // SSD2_CLK6REQ#_N
+};
+
+static void nvme_enable_power(void *unused)
+{
+	gpio_configure_pads(nvme_pwr_seq2, ARRAY_SIZE(nvme_pwr_seq2));
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, nvme_enable_power, NULL);
+
+static const struct pad_config nvme_pwr_seq3[] = {
+	PAD_CFG_GPO(GPP_E03, 1, PLTRST), // M2_SSD1_RST#
+	PAD_CFG_GPO(GPP_B09, 1, PLTRST), // M2_SSD2_RST#
+};
+
+static void nvme_deassert_perst(void *unused)
+{
+	gpio_configure_pads(nvme_pwr_seq3, ARRAY_SIZE(nvme_pwr_seq3));
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, nvme_deassert_perst, NULL);

src/mainboard/system76/ptl/variants/addp6/gpio_early.c

@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	// Model detection
+	PAD_CFG_GPI(GPP_E11, NONE, PLTRST), // BOARD_ID1
+	PAD_CFG_GPI(GPP_E14, NONE, PLTRST), // BOARD_ID2
+	PAD_CFG_GPI(GPP_E15, NONE, PLTRST), // BOARD_ID3
+	PAD_CFG_GPI(GPP_E17, NONE, PLTRST), // BOARD_ID4
+
+	// Debug
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
+
+	// SSD1
+	PAD_CFG_GPO(GPP_B16, 0, PLTRST), // SSD1_PWR_EN
+	PAD_CFG_GPO(GPP_E03, 0, PLTRST), // M2_SSD1_RST#
+	PAD_CFG_GPI(GPP_C14, NONE, DEEP), // SSD1_CLK5REQ#_N
+
+	// SSD2
+	PAD_CFG_GPO(GPP_E08, 0, PLTRST), // SSD2_PWR_EN
+	PAD_CFG_GPO(GPP_B09, 0, PLTRST), // M2_SSD2_RST#
+	PAD_CFG_GPI(GPP_D18, NONE, DEEP), // SSD2_CLK6REQ#_N
+
+	// dGPU
+	PAD_CFG_GPO(GPP_F14, 0, DEEP), // DGPU_PWR_EN
+	PAD_CFG_GPI(GPP_F20, NONE, DEEP), // DGPU_PWRGD
+	PAD_CFG_GPO(GPP_D09, 0, DEEP), // DGPU_RST#
+
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}