MikroLeo project files (schematic, PCB, assembler, emulator/debugger, circuit simulation file, documentation, example of programs etc). MikroLeo is a 4-bit microcomputer developed mainly for educational purposes and distributed for free under open-source licenses.

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Processing Unit with RISCV-32 / RISCV-64 / RISCV-128

MIPS32-based Cpu89 in verilog for Course 10022502 Project

An simple implementation of the Differentiable Neural Harvard Computer

Processing Unit with OpenRISC-32 / OpenRISC-64

dosage is a 20bit single cycle RISC cpu based on harvard architecture

16 Bit, multicore, unicycle processor for general purpose simulated in VHDL. Created as a tool for teaching computer architecture at Federal University of Piauí.

📟 32 bits CPU design

The Agent Meta-Language — a capability-safe language for agents that make agents. Private while dual-use safety, proof, and release boundaries mature.

A Verilog implementation of an 8-bit MIPS processor

A 32-bit Single-Cycle RV32I RISC-V Processor implemented in Verilog HDL, featuring a Harvard Architecture, modular datapath design, hardware Performance Counter Unit (PCU), and functional verification using Icarus Verilog and GTKWave.

16-bit RISC pipeline simulator made in System-C following the classic 5-stage approach: IF, ID, EX, MEM, WB

Implementação didática de um processador de 16 bits multiciclo em Logisim, com arquitetura Harvard, 16 registradores, ULA, unidade de controle e memórias separadas para programa e dados.

Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor

VHDL implementation of a single-cycle Harvard-architecture processor based on the LEGv8 subset introduced by Hennessy and Patterson.

Implementing a subset of ARM instruction set architecture in a multicycle microarchitecture using Xilinx Vivado IDE. The computer architecture followed is Harvard.

C simulator for an 8-bit pipelined Harvard-architecture processor with assembly parsing, instruction encoding, hazard detection, and cycle-by-cycle execution tracing.

32位MIPS CPU设计 - 五级流水线, 哈佛架构, Verilog, FPGA (配套AAOS操作系统)

A parameterized multi-cycle Harvard architecture processor designed from the ground up in Verilog. Developed using a complete RTL design workflow including simulation, linting, synthesis, Sky130 technology mapping, area estimation, static timing analysis, cocotb self-checking testbenches and post synthesis GLS 🖥️.