Minimal implementation of a time-sharing kernel on RISC-V, implemented in Zig, on top of OpenSBI

Trivial RISC-V Linux binary bootloader

Next Generation of Uotan RISC-V Emulator

A RISCV32IMAC Emulator

my progress and contribution yocto project in tessolve

MatteOS: The educational OS for RISC-V

Action that automatically builds the latest VisionFive 2 firmware (OpenSBI + U-Boot), for personal use.

Example of how to write a baremetal Rust program for RV64 which is booted by OpenSBI.

Linux-capable RV64GC RISC-V emulator written in Go with SV39 virtual memory, privilege modes, and device emulation.

xv6-signal-handling: POSIX-style signal implementation for xv6 kernel - SUSTech project of CS302: Operating Systems in Spring 2025 - Score: 100/100

Implementing the “OS in 1,000 Lines” tutorial in Zig

Low-level I/O systems: OpenSBI, bare-metal C, Linux drivers.

A minimal RISC-V 64-bit OS kernel written in Odin, using OpenSBI.

Analysis of RISC-V Linux boot process using QEMU and OpenSBI with architectural state inspection for checkpointing research.

RISC-V BootFlow Playgroun on QEMU

Wrapper to build Sifive Unmatched opensbi, u-boot, kernel with tiny initramfs

RISC-V Open Source Supervisor Binary Interface

C wrapper library for RISC-V SBI calls