- Add initial support for ARMv8A, ARMV7R and ARMV8R #45
GitHub Actions / Test Results
succeeded
Jan 4, 2026 in 0s
All 54 tests pass, 2 skipped in 0s
Annotations
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github-actions / Test Results
2 skipped tests found
There are 2 skipped tests, see "Raw output" for the full list of skipped tests.
Raw output
TC_CoreInstr_WFE
TC_CoreInstr_WFI
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github-actions / Test Results
56 tests found
There are 56 tests, see "Raw output" for the full list of tests.
Raw output
TC_CML1Cache_CleanDCacheByAddrWhileDisabled
TC_CML1Cache_EnDisableDCache
TC_CML1Cache_EnDisableICache
TC_CoreFunc_APSR
TC_CoreFunc_BASEPRI
TC_CoreFunc_Control
TC_CoreFunc_EnDisIRQ
TC_CoreFunc_EncDecIRQPrio
TC_CoreFunc_FAULTMASK
TC_CoreFunc_FPSCR
TC_CoreFunc_FPUType
TC_CoreFunc_IPSR
TC_CoreFunc_IRQPrio
TC_CoreFunc_IRQVect
TC_CoreFunc_MSP
TC_CoreFunc_MSPLIM
TC_CoreFunc_MSPLIM_NS
TC_CoreFunc_PRIMASK
TC_CoreFunc_PSP
TC_CoreFunc_PSPLIM
TC_CoreFunc_PSPLIM_NS
TC_CoreInstr_BKPT
TC_CoreInstr_CLZ
TC_CoreInstr_DMB
TC_CoreInstr_DSB
TC_CoreInstr_ISB
TC_CoreInstr_LoadStoreAcquire
TC_CoreInstr_LoadStoreAcquireExclusive
TC_CoreInstr_LoadStoreExclusive
TC_CoreInstr_LoadStoreUnpriv
TC_CoreInstr_NOP
TC_CoreInstr_RBIT
TC_CoreInstr_REV
TC_CoreInstr_REV16
TC_CoreInstr_REVSH
TC_CoreInstr_ROR
TC_CoreInstr_RRX
TC_CoreInstr_SEV
TC_CoreInstr_SSAT
TC_CoreInstr_USAT
TC_CoreInstr_UnalignedUint16
TC_CoreInstr_UnalignedUint32
TC_CoreInstr_WFE
TC_CoreInstr_WFI
TC_CoreSimd_AbsDif8
TC_CoreSimd_MulAcc32
TC_CoreSimd_Pack16
TC_CoreSimd_PackUnpack
TC_CoreSimd_ParAddSub16
TC_CoreSimd_ParAddSub8
TC_CoreSimd_ParMul16
TC_CoreSimd_ParSat16
TC_CoreSimd_ParSel
TC_CoreSimd_SatAddSub
TC_MPU_Load
TC_MPU_SetClear
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