Add floating point matrix multiply-add widening (FMMLA) intrinsics #409

amilendra · 2025-09-15T12:57:11Z

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FEAT_FPRCVT adds 4 new variants for each FCVTAS, FCVTAU, FCVTMS, FCVTMU, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTZS, and FCVTZU instruction. 1) Half Precision to 32-bit 2) Half Precision to 64-bit 3) Single Precision to 64-bit 4) Double Precision to 32-bit For the Single Precision to 64-bit and Double Precision to 32-bit variants, this patch adds two new intrinsics, that reduce to - Single Precision to 64-bit : <INST> Dd,Sn - Double Precision to 32-bit : <INST> Sd,Dn The intrinsics for conversions from Half Precision are already defined. However they are documented as reducing to the incorrect instruction format; <INST> Hd,Hn, so this patch fixes them to be - Half Precision to 32-bit : <INST> Sd,Hn - Half Precision to 64-bit : <INST> Dd,Hn

tools/intrinsic_db/advsimd.csv

main/acle.md

Lukacma · 2025-09-23T13:49:54Z

main/acle.md

+  svfloat32_t svmmmla[_f32_mf8](svfloat32_t zda, svmfloat8_t zn, svmfloat8_t zm);
+```
+#### FMMLA (widening, FP16 to FP32)
+


This should be in different section as it doesn't operate on modal 8-bit type

This is under the section SVE2 floating-point matrix multiply-accumulate instructions without anything specific to the floating point size, so okay as it is?

main/acle.md

tools/intrinsic_db/advsimd.csv

CarolineConcatto · 2025-09-29T08:23:49Z

main/acle.md

+##### Multiplication of modal 8-bit floating-point matrices
+
+This section is in
+[**Beta** state](#current-status-and-anticipated-changes) and might change or be


Just in case, we are still on Alpha

CarolineConcatto · 2025-09-29T08:26:46Z

main/acle.md

+Modal 8-bit floating-point matrix multiply-accumulate to half-precision.
+```c
+  // Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_F8F16MM)
+  svfloat16_t svmmla[_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn, svmfloat8_t zm, fpm_t fpmd);


s/fpmd/fpm/g

CarolineConcatto · 2025-09-29T08:27:04Z

main/acle.md

+Modal 8-bit floating-point matrix multiply-accumulate to single-precision.
+```c
+  // Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_F8F32MM)
+  svfloat32_t svmmla[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn, svmfloat8_t zm, fpm_t fpmd);


s/fpmd/fpm/g

Adds intrinsic support for the FMMLA matrix multiply-add widening instructions introduced by the 2024 dpISA. FEAT_F8F32MM: Neon/SVE2 FP8 to single-precision FEAT_F8F16MM: Neon/SVE2 FP8 to half-precision FEAT_SVE_F16F32MM: SVE half-precision to single-precision

Lukacma

LGTM

vhscampos · 2025-10-03T09:36:43Z

@all-contributors please add @amilendra for content.

allcontributors · 2025-10-03T09:36:53Z

@vhscampos

I've put up a pull request to add @amilendra! 🎉

@amilendra

Adds @amilendra as a contributor for content. This was requested by vhscampos [in this comment](#409 (comment)) [skip ci] --------- Co-authored-by: allcontributors[bot] <46447321+allcontributors[bot]@users.noreply.github.com>

…nsics" (#415) Reverts #409 I've accidentally merged the PR before full approval.

vhscampos · 2025-10-03T10:26:02Z

I've mistakenly merged the PR too soon, before full approval. I am really sorry for that.

It's been reverted since.

Lukacma · 2025-10-15T11:04:46Z

tools/intrinsic_db/advsimd.csv

 float32x4_t vmlallttq_laneq_f32_mf8_fpm(float32x4_t vd, mfloat8x16_t vn, mfloat8x16_t vm, __builtin_constant_p(lane), fpm_t fpm)	vd -> Vd.4S;vm -> Vn.16B; vm -> Vm.B; 0 <= lane <= 15	FMLALLBB Vd.4S, Vn.16B, Vm.B[lane]	Vd.4S -> result	A64
+
+<SECTION>	Matrix multiplication intrinsics from Armv9.6-A
+float16x4_t vmmlaq_f16_mf8(float16x4_t r, mfloat8x16_t a, mfloat8x16_t b)	r -> Vd.4H;a -> Vn.16B;b -> Vm.16B	FMMLA Vd.4H, Vn.16B, Vm.16B	Vd.4H -> result	A64


These intrinsics are missing FPMR parameter i think

Should be float16x8_t?

Suggested change

float16x4_t vmmlaq_f16_mf8(float16x4_t r, mfloat8x16_t a, mfloat8x16_t b) r -> Vd.4H;a -> Vn.16B;b -> Vm.16B FMMLA Vd.4H, Vn.16B, Vm.16B Vd.4H -> result A64

float16x8_t vmmlaq_f16_mf8(float16x8_t r, mfloat8x16_t a, mfloat8x16_t b) r -> Vd.4H;a -> Vn.16B;b -> Vm.16B FMMLA Vd.4H, Vn.16B, Vm.16B Vd.4H -> result A64

Adds intrinsic support for the FMMLA matrix multiply-add widening instructions introduced by the 2024 dpISA. FEAT_F8F32MM: Neon/SVE2 FP8 to single-precision FEAT_F8F16MM: Neon/SVE2 FP8 to half-precision FEAT_SVE_F16F32MM: SVE half-precision to single-precision Relands PR #409 that was approved, mistakenly merged and subsequently reverted.

CarolineConcatto · 2025-11-12T17:46:52Z

main/acle.md

+Modal 8-bit floating-point matrix multiply-accumulate to half-precision.
+```c
+  // Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_F8F16MM)
+  svfloat16_t svmmla[_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn, svmfloat8_t zm, fpm_t fpm);


Why it needs to have _f16_mf8, does in conflicts with others svmmla?
Could it be only: svmmla[_f16]_fpm

No. I don't think it would conflict with existing intrinsics.
So I suppose similarly svmmla[_f32_mf8]_fpm can be svmmla[_f32]_fpm ?
@AlfieRichardsArm FYI and do you agree? I understand you already have a draft based on the merged #418. Would these changes cause any problems with that?

Hmm will require a bit of reworking but certainly doable. It will require special casing some of our logic, as currently if a set of intrinsics (same mnemonic) differ by 2 argument types we put both in the suffix.

It does seem inconsistent with other intrinsics (like svfloat32_t svmlalltt[_f32_mf8]_fpm) so I would be gently against the change, but not enough to strongly oppose it if @CarolineConcatto prefers it.

I will note though, I would need a decision quite quickly, as support for this is quite urgent, and so we would like it to be in GCC 16 which is closing to contributions imminently.

I guess since we do it that way everywhere else, this ship has failed and we should stay consistent and keep both types.

AlfieRichardsArm reviewed Sep 18, 2025

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tools/intrinsic_db/advsimd.csv Outdated Show resolved Hide resolved

Lukacma reviewed Sep 23, 2025

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amilendra force-pushed the 2025-acle-fmmla branch 2 times, most recently from 17749f2 to 4303ef0 Compare September 24, 2025 14:02

CarolineConcatto reviewed Sep 29, 2025

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amilendra force-pushed the 2025-acle-fmmla branch from 4303ef0 to e102d32 Compare October 1, 2025 09:06

Lukacma approved these changes Oct 1, 2025

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vhscampos merged commit 56fb677 into ARM-software:main Oct 3, 2025
3 of 4 checks passed

allcontributors bot mentioned this pull request Oct 3, 2025

docs: add amilendra as a contributor for content #414

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vhscampos mentioned this pull request Oct 3, 2025

Revert "Add floating point matrix multiply-add widening (FMMLA) intrinsics" #415

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vhscampos added a commit that referenced this pull request Oct 3, 2025

Revert "Add floating point matrix multiply-add widening (FMMLA) intri…

47cd2d6

…nsics" (#415) Reverts #409 I've accidentally merged the PR before full approval.

amilendra mentioned this pull request Oct 7, 2025

Add floating point matrix multiply-accumulate widening intrinsics #418

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Lukacma reviewed Oct 15, 2025

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Amichaxx mentioned this pull request Oct 27, 2025

[Clang][AArch64] Implement widening FMMLA intrinsics llvm/llvm-project#165282

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CarolineConcatto reviewed Nov 12, 2025

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	float16x4_t vmmlaq_f16_mf8(float16x4_t r, mfloat8x16_t a, mfloat8x16_t b) r -> Vd.4H;a -> Vn.16B;b -> Vm.16B FMMLA Vd.4H, Vn.16B, Vm.16B Vd.4H -> result A64
	float16x8_t vmmlaq_f16_mf8(float16x8_t r, mfloat8x16_t a, mfloat8x16_t b) r -> Vd.4H;a -> Vn.16B;b -> Vm.16B FMMLA Vd.4H, Vn.16B, Vm.16B Vd.4H -> result A64

Add floating point matrix multiply-add widening (FMMLA) intrinsics #409

Add floating point matrix multiply-add widening (FMMLA) intrinsics #409

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vhscampos commented Oct 3, 2025

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amilendra commented Sep 15, 2025 •

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