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@AlfieRichardsArm
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AlfieRichardsArm commented Sep 18, 2025

This seems to be missing
- the zeroing forms of all the unary instructions added in S(M|V)E2p2? Such as NOT (zeroing) and REVB (zeroing) and lots more.
- FRECPX
- FSQRT

Will they be added separately?

Corrected offline that these intrinsics are all already present, and will just be simplified by the new instructions.

main/acle.md Outdated
[`<arm_sve.h>`](#arm_sve.h) or [`<arm_sme.h>`](#arm_sme.h)
when `__ARM_FEATURE_SVE2p2` or `__ARM_FEATURE_SME2p2` is defined, respectively.

These intrinsics can only be called from non-streaming code if
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So this is not correct. These instruction can be called in non-streaming mode if we have sme2p2 and sve as well.

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For FIRSTP and LASTP you can also run them in streaming mode if you have sve2p2 and sme.

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I've updated the conditions. Please can you have another look?

@amilendra amilendra force-pushed the 2025-acle-sve-sme2p2 branch from 137ff03 to 7de9269 Compare October 1, 2025 15:02
@amilendra amilendra changed the title Add support for COMPACT/EXPAND and FIRSTP/LASTP intrinsics Add intrinsics for the FEAT_SVE2p2/FEAT_SME2p2 features introduced by the 2024 dpISA Oct 2, 2025
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LGTM

main/acle.md Outdated
`__ARM_FEATURE_SME2p2` feature macro is defined.

They can be called from non-streaming code if the `__ARM_FEATURE_SVE2p2` feature
macro is defined or both the `__ARM_FEATURE_SVE` and `__ARM_FEATURE_SME2p2`
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I am not sure this is correct:
__ARM_FEATURE_SVE and __ARM_FEATURE_SME2p2
should it be:
__ARM_FEATURE_SME and __ARM_FEATURE_SME2p2
Why are you writing that it needs SVE, have you seeing this in the pseudo code from the instruction?

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Yes. Actually that is something I understood from the pseudocode.

For example the psuedocode of COMPACT checks for SVE

It was not immediately obvious to me either, and was pointed out by @Lukacma

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The size that is now available also in sme2p2 and sve is Word and doubleword.
You are adding new ones that are only available for sve2p2 or sme2p2

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Removed those conditions because it is simply repeating information already available in the ISA docs.

main/acle.md Outdated

Scalar index of first/last true predicate element (predicated).

These intrinsics can be called from streaming mode if either of the feature
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I believe this is incorrect. Can you remove these sentences?
They need sve2p2 or sme2p2, there is nothing saying about sve or sme.

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Similar to COMPACT, this is also something I understood from the CheckSVEEnabled pseudocode used by FIRSTP

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That is when the instructions is defined:
if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then
CheckSVEEnabled is how it will run, in streaming mode or sve.

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Removed those conditions because it is simply repeating information already available in the ISA docs.

main/acle.md Outdated

Copy active vector elements to/from lower-numbered elements.

These intrinsics can be called from streaming code only if the
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I believe this sentence are applied to all sve2p2 and sme2p2 instruction you can move it up. After line 13601

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Removed those conditions because it is simply repeating information already available in the ISA docs.

@amilendra amilendra force-pushed the 2025-acle-sve-sme2p2 branch from ff8fbf9 to 777686d Compare October 7, 2025 15:48

``` c
// Variants are also available for:
// [_single_f32_x2]
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@Lukacma Lukacma Oct 14, 2025

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I think we should split this into x2 and x4 variants. I think this might confuse users as to what type to use for arguments.

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I've split them up. Does this look okay?

These instructions are available under features FEAT_SVE2p2 or FEAT_SME2p2.

COMPACT: Copy Active vector elements to lower-numbered elements (Byte/Halfword variants)
EXPAND: Copy lower-numbered vector elements to Active elements (Byte/Halfword/Word/Doubleword variants)
FIRSTP: Scalar index of first true predicate element (predicated) (Byte/Halfword/Word/Doubleword variants)
LASTP: Scalar index of last true predicate element (predicated) (Byte/Halfword/Word/Doubleword variants)
FMUL (multiple and single vector): Multi-vector floating-point multiply by vector
FMUL (multiple vectors): Multi-vector floating-point multiply
1. Change firstp/lastp parameter names to match the register names: op -> pn
2. split the x2 and x4 variants of the FMUL intrinsics
@amilendra amilendra force-pushed the 2025-acle-sve-sme2p2 branch from 5f3e66f to 29f8554 Compare October 24, 2025 12:42
extended in the future.

The intrinsics in this section are defined by the header file
[`<arm_sme.h>`](#arm_sme.h) when `__ARM_FEATURE_SME2p2` is defined.
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Since these instructions do not operate on ZA array, I think they should be in arm_sve.h.

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We need to add these new instructions also:
FRINT32X
FRINT32Z
FRINT64X
FRINT64Z
They are sve2p2 as well

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6 participants