Pinned Loading

1. gpio_soc_kria_kv260 gpio_soc_kria_kv260 Public

   my first project in vivado and verilog i have taken a considerable time in this and still figuring out most of it but hey... came this far

   Verilog

2. RISC_CPU RISC_CPU Public

   16 bit cpu in vhdl

   VHDL

3. axi axi Public

   axi implimentation in vhdl on an FPGA . my first implimentation of a vhdl project on vivado and an attempt to understand RTL,Synthesis, Implimentation deeper

   VHDL