my RISC_CPU is influenced from https://github.com/geekpradd/RISC-CPU-VHDL/tree/main and debugged by claude ai...implemented on vs-code in linux using ghdl and gtkwave.It has a working ALU with sub,add,and nand components other than that it has a working RAM and multiple registers as per RISC architecture.the wave given below is my output/observation