RISC_CPU/work-obj93.cf at main · AneeshV1202/RISC_CPU · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
v 4
file . "tb/cpu_tb.vhd" "f32affc2e5477f5f3167d921cb3166dbae480f59" "20251029123214.387":
  entity cpu_tb at 1( 0) + 0 on 41;
  architecture testbench of cpu_tb at 8( 129) + 0 on 42;
file . "src/register_file.vhd" "4869f809c437012c82d430a895ebf39307281300" "20251029123214.386":
  entity register_file at 1( 0) + 0 on 39;
  architecture arch of register_file at 20( 561) + 4 on 40;
file . "src/register_1.vhd" "0da17a41d7da4f2b9383bf210f0aaf38346c9231" "20251029123214.386":
  entity register_1bit at 1( 0) + 0 on 37;
  architecture arch of register_1bit at 15( 242) + 4 on 38;
file . "src/register_16bit.vhd" "4a003881c36d830f67c5fa41e37c2e73cfa5bfae" "20251029123214.385":
  entity register_16bit at 1( 0) + 0 on 35;
  architecture arch of register_16bit at 17( 283) + 0 on 36;
file . "src/RAM.vhd" "8d115f586e5ec99b7c8beae82576528b7d1b8a94" "20251029123214.385":
  entity ram at 1( 0) + 0 on 33;
  architecture rt1 of ram at 14( 282) + 0 on 34;
file . "src/controller.vhd" "eb34b73ea3acadd6d879bac36456711050b59607" "20251029123214.385":
  entity controller at 1( 0) + 0 on 31;
  architecture behave of controller at 22( 771) + 0 on 32;
file . "src/2__1mux.vhd" "be967b5dadb8885a25dc1330361471b00ccada8f" "20251029123214.383":
  entity twobyonemux1 at 2( 1) + 0 on 29;
  architecture arch of twobyonemux1 at 14( 201) + 0 on 30;
file . "src/alu/sub16bit.vhd" "3995e60bcbddaa2b0c0108bfb44c07e93b542974" "20251029123214.383":
  entity sub16bit at 1( 0) + 0 on 27;
  architecture subhv of sub16bit at 16( 246) + 0 on 28;
file . "src/alu/nand_16.vhd" "de24065c1d5700fda520f78eb13e4aa7f2ec6741" "20251029123214.382":
  entity nand_16 at 1( 0) + 0 on 25;
  architecture behav of nand_16 at 16( 256) + 4 on 26;
file . "src/alu/KS16bit.vhd" "e9dc1620f785ce2bcaaff20f1dfb4d542f9eebcd" "20251029123214.382":
  entity ks16bit at 1( 0) + 0 on 19;
  entity node at 13( 257) + 0 on 20;
  architecture node_bhv of node at 24( 448) + 0 on 21;
  entity buffer_block at 30( 584) + 0 on 22;
  architecture buffer_bhv of buffer_block at 41( 777) + 0 on 23;
  architecture behaviour of ks16bit at 47( 894) + 0 on 24;
file . "src/alu/ALU.vhd" "ab846cd25e0e27095de140c0b2c1943aed460e7a" "20251029123214.381":
  entity alu at 1( 0) + 0 on 17;
  architecture behavioral of alu at 16( 320) + 0 on 18;
file . "src/alu/adder16bit.vhd" "978868bd9dd32c71e649078c0e8afca98bf24ce5" "20251029123214.380":
  entity adder16bit at 1( 0) + 0 on 15;
  architecture addbhv of adder16bit at 12( 210) + 0 on 16;
file . "src/alu/4_or.vhd" "9a0ad211ea9472948d33bf17ccdc2e1a44c3d649" "20251029123214.380":
  entity four_or at 1( 0) + 0 on 13;
  architecture or4_bhv of four_or at 15( 210) + 0 on 14;
file . "src/alu/2_nand.vhd" "a7cd73772d766c565373f5403bb620dc89d57b5f" "20251029123214.380":
  entity two_nand at 1( 0) + 0 on 11;
  architecture behav of two_nand at 16( 217) + 4 on 12;