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[CHERI] Integrate the RISCV Y register file definition #257

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Merged
merged 2 commits into from
Oct 8, 2025
Merged

[CHERI] Integrate the RISCV Y register file definition #257

merged 2 commits into from
Oct 8, 2025

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@resistor resistor commented Oct 8, 2025

  • [AsmMatcher] Add support for conflicting features
  • [CHERI] Integrate the RISCV Y version of the CHERI register file.

@arichardson @sbaranga-arm @resistor
[AsmMatcher] Add support for conflicting features
b54f39b 
This helps avoiding diagnostics for instructions that could never be
selected and is required for RISC-V CHERI support.
An example here are the CHERI mode-dependent instructions where we have
loads/stores that are identical other than the register class for the
base register and have predicates that can never both be set. To avoid
nonsensical error messages, we should only use the candidate
instructions with the currently available feature bits.

For RVY (CHERI), loads and stores are mode-dependent, using either a
YLEN register or a XLEN register as the base. Prior to the
standardization process CHERI assembly used c-prefixed register names
for capabilities, so we had the following syntax for RISC-V compatible
mode and CHERI pure-capability mode:

lw x4, 0(c3)  # capability mode: use new `CLW` tablegen instruction
lw x4, 0(x3)  # integer mode: use existing `LW` tablegen instruction

During the standardization this was changed to keep the same register
name in both modes, so now we have `lw x4, 0(x3)` in both modes but we
have to select between two instructions: one using the normal GPR
register class and one using the YGPR register class.
We now have a choice between two instructions `LW` and `LW_Y` that have
predicates that can never both be true, so we should avoid reporting
missing predicates or wrong operands for the "unreachable" instruction.

This change was taken from Morello LLVM with a few minor comment
clarifications and changes to naming of variables.

Co-authored-by: Silviu Baranga <[email protected]>
@resistor resistor merged commit 7a0b1e2 into CHERIoT-Platform:cheriot Oct 8, 2025
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resistor commented Oct 8, 2025

Rolling this back as it caused some issues with asm(...) variable declarations in CheriotRTOS.

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2 participants

@resistor @arichardson