Generate simulation main.cc from the user's design #134
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Contributor
robtaylor
commented
Jul 30, 2025
robtaylor
commented
- Update sim infrastructure so it all lives in chipflow-lib
- Make wiring up ports common code and fix invert case
- feat: Enable configuring of package pin allocation from the package definition
- Add openframe package support
- Wire up the extra signals for sky130 io
- fix lint issues
- Reduce API surface
- Fix up tests for reduce API
- Update package pins documentation
- Add amaranth: UnusedElaboratable=no to silicon step
- Make DriveMode sky130 specific for now
- Fix issue with Package type name
- Fix title for package pins docs
- Fixes for test suite
- Set pipefail when submitting
- Bring out all _oe/_oeb/_dm lines so easy for backend to wire up
- Sky130: Split dm into dm0,dm1,dm2
- Sky130: inp_dis is an output...
- Allow input enable for all processes
- Correct comments in openframe pin map
- After discussion, remove oe_n and ie_n, handle in backend
- Fix lint issues
- Enable various pyright checks and fix code for them
- Initialise ie to -1
- When port is not using ie, it should be connected to oe inverted
- Fix so always oes on pad side, and fix dm initialisation
- Use a gpio for our reset, as we don't know much about resetb yet
- Tidy up pad side OE logic
- Generalise adding an Amaranth annotation via a TypedDict
- wip
- Fix some lint issues
- sim interface annotation working
- wip: now somehat generating flash load
- wip
- wip
- Enable c++ model parameterisation, apply to gpio
- gitignore docs/autoapi
- loading data to a simulation model now supported
- Support attaching metadata during elaboration
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gatecat
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Jul 31, 2025
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gatecat
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Contributor
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This seems to need a rebase - I think it's still entangled with the now-merged shell-support stuff |
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Should be good now! |
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gatecat
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Sep 9, 2025
ports. This allows port signatures to be annotated as to the kind and behaviour of that port (e.g. its SPI, its I2C..) to allow the automatic assembling of a simulation model for the IC design.
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