feat(decode): implement RV32I arithmetic operation instruction

Author: EmbroiderSnow

sim/src/decode.c

@@ -37,7 +37,7 @@ static void decode_operand(Decode *s, int *rd, uint64_t *src1, uint64_t *src2, u
     int rs2 = BITS(i, 24, 20);
     *rd     = BITS(i, 11,  7);
     switch(type) {
-        // TODO: TYPE_R
+        case TYPE_R: src1R(); src2R();         break;
         case TYPE_I: src1R();          immI(); break;
         case TYPE_U:                   immU(); break;
         case TYPE_J:                   immJ(); break;
@@ -98,6 +98,16 @@ void decode_exec(Decode *s){
     INSTPAT("??????? ????? ????? 111 ????? 00100 11", andi   , I, R(rd) = src1 & imm);
     INSTPAT("??????? ????? ????? 000 ????? 00110 11", addiw  , I, R(rd) = SEXT((int32_t)src1 + (int32_t)imm, 32));
     // ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND
+    INSTPAT("0000000 ????? ????? 000 ????? 01100 11", add    , R, R(rd) = src1 + src2);
+    INSTPAT("0100000 ????? ????? 000 ????? 01100 11", sub    , R, R(rd) = src1 - src2);
+    INSTPAT("0000000 ????? ????? 001 ????? 01100 11", sll    , R, R(rd) = src1 << (src2 & 0x3f));
+    INSTPAT("0000000 ????? ????? 010 ????? 01100 11", slt    , R, R(rd) = (int64_t)src1 < (int64_t)src2);
+    INSTPAT("0000000 ????? ????? 011 ????? 01100 11", sltu   , R, R(rd) = src1 < src2);
+    INSTPAT("0000000 ????? ????? 100 ????? 01100 11", xor    , R, R(rd) = src1 ^ src2);
+    INSTPAT("0000000 ????? ????? 101 ????? 01100 11", srl    , R, R(rd) = src1 >> (src2 & 0x3f));
+    INSTPAT("0100000 ????? ????? 101 ????? 01100 11", sra    , R, R(rd) = (int64_t)src1 >> (src2 & 0x3f));
+    INSTPAT("0000000 ????? ????? 110 ????? 01100 11", or     , R, R(rd) = src1 | src2);
+    INSTPAT("0000000 ????? ????? 111 ????? 01100 11", and    , R, R(rd) = src1 & src2);
     // ADDW, SUBW, SLLW, SRLW, SRAW
     // FENCE, FENCE.I
     // ECALL