Add ML4EP project description and new proposals from hls4ml

_gsocprojects/2025/project_ML4EP.md

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+---
+project: ML4EP
+layout: default
+logo:
+description: |
+  ML4EP is a project of the CERN [SFT group](https://ep-dep-sft.web.cern.ch) focused on developing common machine learning (ML) software tools to support HEP experiments. The current  ongoing activities are:  
+  - Designing  generic generative ML models for fast simulation of calorimeter showers
+  - Developing ML software for efficient inference in C++, such as [SOFIE](https://root.cern/manual/tmva/#sofie) and creating interfaces between external provided ML software and HEP software like [ROOT](https://root.cern)
+  - Building tools for ML inferfence in FPGA like [hls4ml](https://fastmachinelearning.org/hls4ml/)
+  - Developing common libraries for model compression and quantization, facilitating optimized ML workflow and porting of ML HEP applications in a real time environment. 
+summary: |
+  ML4EP is a project of the CERN [SFT group](https://ep-dep-sft.web.cern.ch) focused on developing common machine learning (ML) software tools to support HEP experiments.
+---
+
+{% include gsoc_project.ext %}

_gsocproposals/2025/proposal_ML4EP_Google_XLS_in_hls4ml.md

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+---
+title: Integrating Support for Google XLS in HLS4ML
+layout: gsoc_proposal
+project: ML4EP
+year: 2025
+organization: CERN
+difficulty: medium/high
+duration: 350
+mentor_avail: Flexible
+project_mentors:
+  - email: [email protected] 
+    organization: CERN
+    first_name: Vladimir
+    last_name: Loncar
+    is_preferred_contact: yes
+  - email: [email protected]
+    first_name: Dimitrios
+    last_name: Danopoulos
+    organization: CERN
+---
+
+# Description
+
+Google XLS (Accelerated Hardware Synthesis) is an advanced open-source framework for high-level hardware design, offering flexible and efficient synthesis for FPGA and ASIC applications. By integrating XLS into HLS4ML, a framework for translating machine learning models into FPGA-friendly code, we can leverage XLS’s optimizing compiler and domain-specific language to improve resource efficiency, performance, and portability. This integration will enable seamless generation of highly optimized hardware implementations for ML models while maintaining the ease of use that HLS4ML provides.
+
+HLS4ML currently supports traditional HLS tools like Vivado HLS and Intel HLS, but adding XLS can bring further benefits such as better compilation times, improved hardware efficiency, and wider vendor compatibility. This project will focus on developing an interface between HLS4ML and XLS, allowing ML models to be translated into XLS IR and synthesized efficiently.
+
+# Task Ideas
+
+  * Develop a backend in HLS4ML that translates neural network layers into XLS Intermediate Representation (IR).
+  * Implement the key ML operations (e.g., matrix multiplications, activations, and pooling) via XLS's DSLX language and map them to HLS4ML operations.
+  * Benchmark and compare performance, resource utilization, and synthesis results against existing HLS4ML backends.
+  * Extend HLS4ML’s configuration options to allow selection of XLS as a backend, ensuring ease of integration.
+
+# Expected Results
+
+  * A prototype of a backend in HLS4ML supporting XLS-based synthesis.
+  * Conversion scripts to map ML operations to XLS IR.
+  * Performance evaluation of XLS and existing HLS backends.
+  * Documentation and tutorials for using XLS with HLS4ML.
+
+## Requirements
+  * Proficiency in Python and C++.
+  * Knowledge of hardware and compiler design.
+  * Basic familiarity with neural networks.
+  * Familiarity with version control systems like Git/GitHub.
+
+
+## Links
+  * [hls4ml documentation](https://fastmachinelearning.org/hls4ml/)
+  * [hls4ml Repository](https://github.com/fastmachinelearning/hls4ml)
+  * [Google XLS documentation](https://google.github.io/xls/)
+  * [Google XLS repository](https://github.com/google/xls)

_gsocproposals/2025/proposal_ML4EP_hls4ml_ip_split.md

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+---
+title: Optimizing Model Splitting in hls4ml for Efficient Multi-Graph Inference
+layout: gsoc_proposal
+project: ML4EP
+year: 2025
+organization: CERN
+difficulty: medium
+duration: 350
+mentor_avail: Flexible
+project_mentors:
+  - email: [email protected] 
+    organization: CERN
+    first_name: Vladimir
+    last_name: Loncar
+    is_preferred_contact: yes
+  - email: [email protected]
+    first_name: Dimitrios
+    last_name: Danopoulos
+    organization: CERN
+---
+
+# Description
+hls4ml is an open-source tool that enables the deployment of machine learning (ML) models on FPGAs using High-Level Synthesis (HLS). It automatically converts pre-trained models from popular deep learning frameworks (e.g., Keras, PyTorch, and ONNX) into optimized firmware for FPGA-based inference.
+
+Traditionally, the entire ML model is synthesized as a monolithic graph, which can lead to long synthesis times and complicated debugging, especially for large model topologies. Splitting the model graph at specified layers into independent subgraphs allows for parallel synthesis and step-wise optimization. However, finding the 'optimal' splitting points and optimizing FIFO buffers in between the subgraphs remains a challenge, especially when dealing with dynamic streaming architectures.
+
+This project aims to investigate optimal splitting strategies for complex ML models in hls4ml, focusing on efficient FIFO depth optimization across multi-graph designs. The goal is to develop methodologies that can be integrated into hls4ml to enable automated and optimal graph splitting for improved performance.
+
+## Task ideas
+The contributor will start by familiarizing themselves with hls4ml and building ML models using multi-graph designs. They will implement profiling techniques (e.g., VCD logging) to measure FIFO occupancy and backpressure in order to develop a FIFO optimization strategy for multi-graph designs. They will also investigate multi-objective optimization algorithms to determine optimal splitting points based on subgraph resource usage or dataflow patterns. Finally, they will integrate these methodologies with hls4ml and run benchmarks to validate improvements in latency, resource utilization, etc.
+
+## Expected results and milestones
+ * **Familiarization with hls4ml**: Understand the hls4ml workflow, including synthesis, and simulation.
+ * **Research and Evaluation**: Explore FIFO profiling and optimization strategies along with algorithms to partition the model graph given specific optimization objectives.
+ * **Validation**: Benchmark against monolithic implementations and compare differences in latency and resource utilization.
+
+## Requirements
+  * Proficiency with computer architecture, FPGA design and simulation tools (e.g., Vivado)
+  * Experience with Python
+  * Understanding of ML concepts is beneficial.
+  * Familiarity with version control systems like Git/GitHub.
+
+
+## Links
+  * [hls4ml documentation](https://fastmachinelearning.org/hls4ml/)
+  * [hls4ml Repository](https://github.com/fastmachinelearning/hls4ml)
+  * [Vivado Design Implementation](https://docs.amd.com/r/en-US/ug949-vivado-design-methodology/Design-Implementation)

_gsocproposals/2025/proposal_TMVA-SOFIE-GPU.md

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 ---
 title: TMVA SOFIE - GPU Support for Machine Learning Inference
 layout: gsoc_proposal
-project: ROOT
+project: ML4EP
 year: 2025
 organization: CERN
 difficulty: medium

_gsocproposals/2025/proposal_TMVA-SOFIE-HLS4ML.md

@@ -1,7 +1,7 @@
 ---
 title: TMVA SOFIE - HLS4ML Integration for Machine Learning Inference
 layout: gsoc_proposal
-project: ROOT
+project: ML4EP
 year: 2025
 organization: CERN
 difficulty: medium

_gsocproposals/2025/proposal_TMVA-SOFIE-TF_JAX.md

@@ -1,7 +1,7 @@
 ---
 title: TMVA SOFIE - Enhancing Keras Parser and JAX/FLAX Integration
 layout: gsoc_proposal
-project: ROOT
+project: ML4EP
 year: 2025
 organization: CERN
 difficulty: medium