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@MassiveBattlebotsFan MassiveBattlebotsFan commented Oct 3, 2025

In draft until I can figure out why math_unit_flags hates my guts (occasional multi-driven net weirdness). Fixed.

Stuff that's changed:

  • The FPU is enabled.
  • divider32.vhdl is actually a divider.
  • The latch system is more programmable.
  • Every unit is now an adder, instead of half of them being subtractors.
  • Input B can be inverted on a per-unit basis, to let every unit be a subtractor.
  • The FPU halts when the next math cycle number is equal to the cycle compare register.
  • Dividers can be configured to act as multipliers.

@MassiveBattlebotsFan
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This should be good to go now from a functionality perspective, although it definitely needs documentation.

@MassiveBattlebotsFan MassiveBattlebotsFan marked this pull request as ready for review October 22, 2025 15:25
@MassiveBattlebotsFan
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Hmm, it doesn't appear to fit on 100T platforms. Looking at optimizations to see if I can make it work.

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