Interrupt management optimize and minor fixes

core/embed/bootloader/main.c

@@ -648,6 +648,23 @@ int main(void) {
                       // mpu may already running
   mpu_ctrl(sectrue);  // ensure enabled
 
+  // disable all external communication or user input irq
+  // will be re-enabled later by calling their init function
+  // bluetooth uart
+  HAL_NVIC_DisableIRQ(UART4_IRQn);
+  HAL_NVIC_ClearPendingIRQ(UART4_IRQn);
+  // bluetooth spi
+  HAL_NVIC_DisableIRQ(SPI2_IRQn);
+  HAL_NVIC_ClearPendingIRQ(SPI2_IRQn);
+  HAL_NVIC_DisableIRQ(EXTI15_10_IRQn);
+  HAL_NVIC_ClearPendingIRQ(EXTI15_10_IRQn);
+  // usb
+  HAL_NVIC_DisableIRQ(OTG_HS_IRQn);
+  HAL_NVIC_ClearPendingIRQ(OTG_HS_IRQn);
+
+  __enable_irq();
+  __enable_fault_irq();
+
   lcd_ltdc_dsi_disable();
   sdram_reinit();
   // lcd_para_init(DISPLAY_RESX, DISPLAY_RESY, LCD_PIXEL_FORMAT_RGB565);
@@ -789,12 +806,10 @@ int main(void) {
     }
 
     display_clear();
-
     bus_fault_disable();
 
-    // Disable SPI Chip Select interrupt for compatibility with older firmware
-    // versions
-    spi_disable_cs_irq();
+    __disable_irq();
+    __disable_fault_irq();
 
     // enable firmware region
     mpu_config_firmware(sectrue, sectrue);

core/embed/bootloader/startup.s

@@ -5,6 +5,10 @@
   .global reset_handler
   .type reset_handler, STT_FUNC
 reset_handler:
+
+  // disable all irq and exceptions
+  cpsid if
+
   // setup environment for subsequent stage of code
   ldr r0, =axiram_start // r0 - point to beginning of axiram
   ldr r1, =axiram_end   // r1 - point to byte after the end of axiram
@@ -27,12 +31,6 @@ reset_handler:
   ldr r1, = __stack_chk_guard
   str r0, [r1]
 
-  // re-enable exceptions
-  // according to "ARM Cortex-M Programming Guide to Memory Barrier Instructions" Application Note 321, section 4.7:
-  // "If it is not necessary to ensure that a pended interrupt is recognized immediately before
-  // subsequent operations, it is not necessary to insert a memory barrier instruction."
-  cpsie f
-
   // enter the application code
   bl main
 

core/embed/firmware/main.c

@@ -94,8 +94,8 @@ static void copyflash2sdram(void) {
 }
 
 int main(void) {
-  extern uint32_t _vector_offset;
-  SCB->VTOR = (uint32_t)&_vector_offset;
+  SystemCoreClockUpdate();
+  dwt_init();
 
   mpu_config_boardloader(sectrue, secfalse);
   mpu_config_bootloader(sectrue, secfalse);
@@ -104,8 +104,24 @@ int main(void) {
                       // mpu may already running
   mpu_ctrl(sectrue);  // ensure enabled
 
-  SystemCoreClockUpdate();
-  dwt_init();
+  // disable all external communication or user input irq
+  // will be re-enabled later by calling their init function
+  // bluetooth uart
+  HAL_NVIC_DisableIRQ(UART4_IRQn);
+  HAL_NVIC_ClearPendingIRQ(UART4_IRQn);
+  // bluetooth spi
+  HAL_NVIC_DisableIRQ(SPI2_IRQn);
+  HAL_NVIC_ClearPendingIRQ(SPI2_IRQn);
+  HAL_NVIC_DisableIRQ(EXTI15_10_IRQn);
+  HAL_NVIC_ClearPendingIRQ(EXTI15_10_IRQn);
+  // usb
+  HAL_NVIC_DisableIRQ(OTG_HS_IRQn);
+  HAL_NVIC_ClearPendingIRQ(OTG_HS_IRQn);
+
+  // re-enable global irq
+  __enable_irq();
+  __enable_fault_irq();
+
   lcd_ltdc_dsi_disable();
   sdram_reinit();
   // lcd_para_init(DISPLAY_RESX, DISPLAY_RESY, LCD_PIXEL_FORMAT_RGB565);

core/embed/firmware/startup.S

@@ -6,21 +6,15 @@
   .type reset_handler, STT_FUNC
 reset_handler:
 
-// The following loading of VTOR address only works if T1 bootloader was built with PRODUCTION=0
-// or the firmware was properly signed. All other variants end up in hard fault due to MPU
-// (cf mpu_config_firmware in legacy bootloader)
-
-#if defined TREZOR_MODEL_1
   cpsid if
   ldr r0, =0xE000ED08  // r0 = VTOR address
-  ldr r1, =0x08010400  // r1 = FLASH_APP_START
+  ldr r1, =_vector_offset  // r1 = FLASH_APP_START
   str r1, [r0]         // assign
 
   ldr r0, =_estack      // r0 = stack pointer
   msr msp, r0           // set stack pointer
   dsb
   isb
-#endif
 
   // setup environment for subsequent stage of code
   ldr r0, =axiram_start // r0 - point to beginning of axiram
@@ -44,16 +38,6 @@ reset_handler:
   ldr r1, = __stack_chk_guard
   str r0, [r1]
 
-  // re-enable exceptions
-  // according to "ARM Cortex-M Programming Guide to Memory Barrier Instructions" Application Note 321, section 4.7:
-  // "If it is not necessary to ensure that a pended interrupt is recognized immediately before
-  // subsequent operations, it is not necessary to insert a memory barrier instruction."
-#if defined TREZOR_MODEL_T || defined TREZOR_MODEL_R
-  cpsie f
-#elif defined TREZOR_MODEL_1
-  cpsie if
-#endif
-
   // enter the application code
   bl main
 

core/embed/firmware/version.h

@@ -3,7 +3,7 @@
 #define VERSION_PATCH 99
 #define VERSION_BUILD 99
 
-#define FIX_VERSION_MAJOR VERSION_MINOR
+#define FIX_VERSION_MAJOR VERSION_MAJOR
 #define FIX_VERSION_MINOR VERSION_MINOR
 #define FIX_VERSION_PATCH VERSION_PATCH
 #define FIX_VERSION_BUILD VERSION_BUILD

core/embed/trezorhal/usart.c

@@ -89,7 +89,6 @@ void ble_usart_init(void) {
   hdma_tx.Init.Priority = DMA_PRIORITY_MEDIUM;
 
   HAL_DMA_Init(&hdma_tx);
-
   __HAL_LINKDMA(huart, hdmatx, hdma_tx);
 
   hdma_rx.Instance = UARTx_RX_DMA_STREAM;
@@ -105,17 +104,22 @@ void ble_usart_init(void) {
   hdma_rx.Init.Priority = DMA_PRIORITY_MEDIUM;
 
   HAL_DMA_Init(&hdma_rx);
-
   __HAL_LINKDMA(huart, hdmarx, hdma_rx);
 
+  // clear all on going tx/rx
+  HAL_UART_Abort(huart);
+
   /*##-4- Configure the NVIC for DMA #########################################*/
   NVIC_SetPriority(UARTx_DMA_RX_IRQn, IRQ_PRI_DMA);
+  HAL_NVIC_ClearPendingIRQ(UARTx_DMA_RX_IRQn);
   HAL_NVIC_EnableIRQ(UARTx_DMA_RX_IRQn);
 
   NVIC_SetPriority(UARTx_DMA_TX_IRQn, IRQ_PRI_DMA);
+  HAL_NVIC_ClearPendingIRQ(UARTx_DMA_TX_IRQn);
   HAL_NVIC_EnableIRQ(UARTx_DMA_TX_IRQn);
 
   NVIC_SetPriority(UART4_IRQn, IRQ_PRI_UART);
+  HAL_NVIC_ClearPendingIRQ(UART4_IRQn);
   HAL_NVIC_EnableIRQ(UART4_IRQn);
 
   __HAL_UART_ENABLE_IT(huart, UART_IT_IDLE);