configs: reduce UARTLite console PIO latency for Xiangshan bare-metal runs

[jensen-yan]

Summary

• reduce Xiangshan UARTLite PIO latency to 1ns in makeXiangshanPlatformSystem
• keep debug printf/console output from dominating short bare-metal runs
• treat UART console as near-functional debug plumbing rather than a performance target

Motivation

On local macOS runs, short bare-metal workloads such as CoreMark can spend a disproportionate amount of simulated time in UART-backed console output. This makes printf-heavy debug output distort IPC/CPI and overall runtime much more than desired for CPU-focused analysis.

This change keeps the model simple and makes the console behavior closer to a fast debug channel, which is more aligned with how we use it in practice.

Validation

Ran:

./build/RISCV/gem5.opt ./configs/example/kmhv3.py \
  --disable-difftest \
  --raw-cpt \
  --generic-rv-cpt=/Users/yanyue/workspace/cursor-test/ready-to-run/coremark-2-iteration.bin

Observed after this change:

• simTicks = 199509624
• system.cpu.numCycles = 599129
• system.cpu.ipc = 1.107324
• system.cpu.cpi = 0.903078

Compared with the original behavior, the short CoreMark run spent substantially less time in console-related UART accesses.

Summary by CodeRabbit

• Bug Fixes
  • Optimized debug console output timing to prevent dominance during short bare-metal simulations, improving overall output behavior.

[coderabbitai]

No actionable comments were generated in the recent review. 🎉

ℹ️ Recent review info

⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: fd8a535d-3770-4bc1-a74c-03b717196c0b

📥 Commits

Reviewing files that changed from the base of the PR and between 6cc70c4 and a66fa98.

📒 Files selected for processing (1)

• configs/common/FSConfig.py

---

📝 Walkthrough

Walkthrough

A single latency configuration parameter is added to the UART initialization in the platform system setup. The change assigns a 1-nanosecond delay to the UART I/O latency to regulate debug console output timing during bare-metal execution.

Changes

Cohort / File(s)	Summary
UART Latency Configuration configs/common/FSConfig.py	Added uartlite.pio_latency = '1ns' assignment during UART initialization to control I/O timing for debug output in bare-metal runs.

Estimated code review effort

🎯 1 (Trivial) | ⏱️ ~2 minutes

Poem

🐰 A whisker of time, just one nanosecond slight,
Tames the chatty UART's relentless midnight flight,
Console output flows with measured grace,
Bare-metal debugging finds its proper pace! ✨

🚥 Pre-merge checks | ✅ 2 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 0.00% which is insufficient. The required threshold is 80.00%.	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (2 passed)

Check name	Status	Explanation
Description Check	✅ Passed	Check skipped - CodeRabbit’s high-level summary is enabled.
Title check	✅ Passed	The title directly and specifically describes the main change: reducing UARTLite console PIO latency for Xiangshan bare-metal runs, which matches the file modification in FSConfig.py.

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✨ Finishing Touches

• 📝 Generate docstrings (stacked PR)
• 📝 Generate docstrings (commit on current branch)

🧪 Generate unit tests (beta)

• Create PR with unit tests
• Commit unit tests in branch yy/fast-uartlite-console

📝 Coding Plan

• Generate coding plan for human review comments

---

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[github-actions]

🚀 Coremark Smoke Test Results

Branch	IPC	Change
Base (xs-dev)	2.2665	-
This PR	2.3450	📈 +0.0785 (+3.46%)

✅ Difftest smoke test passed!

[XiangShanRobot]

[Generated by GEM5 Performance Robot]
commit: a66fa98
workflow: gem5 Align BTB Performance Test(0.3c)

Align BTB Performance

Overall Score

	PR	Master	Diff(%)
Score	18.27	18.26	+0.02 🟢

[XiangShanRobot]

[Generated by GEM5 Performance Robot]
commit: a66fa98
workflow: gem5 Align BTB Performance Test(0.3c)

Align BTB Performance

Overall Score

	PR	Master	Diff(%)
Score	18.27	18.26	+0.02 🟢