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configs: reduce UARTLite console PIO latency for Xiangshan bare-metal runs #789

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configs: reduce UARTLite console PIO latency for Xiangshan bare-metal runs #789

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4 changes: 4 additions & 0 deletions configs/common/FSConfig.py
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Original file line number Diff line number Diff line change
Expand Up @@ -682,6 +682,10 @@ def makeXiangshanPlatformSystem(mem_mode, mdesc=None, np=1, ruby=False):
self.bridge.cpu_side_port = self.membus.mem_side_ports

self.uartlite = UartLite()
# Keep debug console output from dominating short bare-metal runs.
# We do not study UART timing here, so prefer a near-functional UART for
# printf-heavy debug/program output.
self.uartlite.pio_latency = '1ns'
self.uartlite.pio = self.iobus.mem_side_ports

self.lint = Clint()
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