submodule(difftest): refactor DiffTop, PhyReg and Refill

Makefile

@@ -153,8 +153,7 @@ endif
 
 # public args sumup
 RELEASE_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS)
-DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS)
-override PLDM_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS)
+override DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS)
 
 # co-simulation with DRAMsim3
 ifeq ($(WITH_DRAMSIM3),1)
@@ -196,12 +195,13 @@ endif
 
 # emu for the release version
 RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem
-DEBUG_ARGS   += --enable-difftest
-override PLDM_ARGS += --enable-difftest
+ifeq ($(FPGA), 1)
+override DEBUG_ARGS	+= --fpga-platform --disable-all --remove-assert
+else
+override DEBUG_ARGS	+= --enable-difftest
+endif
 ifeq ($(RELEASE),1)
 override SIM_ARGS += $(RELEASE_ARGS)
-else ifeq ($(PLDM),1)
-override SIM_ARGS += $(PLDM_ARGS)
 else
 override SIM_ARGS += $(DEBUG_ARGS)
 endif
@@ -214,8 +214,8 @@ override SIM_ARGS += $(foreach c,$(call splitcomma,$(FIRRTL_COVER)),--extract-$(
 endif
 
 # use RELEASE_ARGS for TopMain by default
-ifeq ($(PLDM), 1)
-TOPMAIN_ARGS += $(PLDM_ARGS)
+ifeq ($(or $(PLDM),$(FPGA)), 1)
+TOPMAIN_ARGS += $(DEBUG_ARGS)
 else
 TOPMAIN_ARGS += $(RELEASE_ARGS)
 endif

scripts/xspdb/xscmd/cmd_difftest.py

@@ -70,11 +70,10 @@ def api_init_ref(self, force=False):
             self.df.finish_device()
             self.df.GoldenMemFinish()
             self.df.difftest_finish()
-            self.df.difftest_init()
+            self.api_init_mem()
+            self.df.difftest_init(True, self.exec_bin_file)
             self.difftest_stat = self.df.GetDifftest(0).dut
         self.df.init_device()
-        self.df.GoldenMemInit()
-        self.df.init_nemuproxy(0)
         self.difftest_ref_is_inited = True
         return True
 
@@ -326,6 +325,19 @@ def api_difftest_get_instance(self, instance=0):
         """
         return self.df.GetDifftest(instance)
 
+    def do_xdifftest_turn_on(self, arg):
+        """Turn on the difftest diff
+
+        Args:
+            arg (string): Turn on or off
+        """
+        if arg.strip() == "on":
+            self.api_set_difftest_diff(True)
+        elif arg.strip() == "off":
+            self.api_set_difftest_diff(False)
+        else:
+            error("usage: xdifftest_turn_on <on|off>")
+
     def complete_xdifftest_turn_on(self, text, line, begidx, endidx):
         return [x for x in ["on", "off"] if x.startswith(text)] if text else ["on", "off"]
 

scripts/xspdb/xspdb.py

@@ -86,7 +86,7 @@ def __init__(self, dut, default_file=None,
         self.df.InitFlash("")
         self.xspdb_init_bin = "xspdb_flash_init.bin"
         self.flash_bin_file = None
-        self.df.difftest_init()
+        self.df.difftest_init(False, self.mem_size)
         self.difftest_stat =  df.GetDifftest(0).dut
         self.difftest_flash = df.GetFlash()
         self.register_map = OrderedDict()
@@ -101,17 +101,17 @@ def __init__(self, dut, default_file=None,
     def check_is_need_trace(self):
         if getattr(self, "__xspdb_need_fast_trace__", False) is True:
             setattr(self, "__xspdb_need_fast_trace__" ,False)
-            info("Force set trace") 
+            info("Force set trace")
             self.set_trace()
         if self.interrupt is True:
             if getattr(self, "__xspdb_set_traced__", None) is None:
-                self.setattr(self, "__xspdb_set_traced__", True) 
+                self.setattr(self, "__xspdb_set_traced__", True)
                 info("Find interrupt, set trace")
                 self.set_trace()
         return False
 
     def __init_pdb(self, args):
-        if args.log: 
+        if args.log:
             self.api_log_enable_log(True)
         if args.log_file:
             self.api_log_set_log_file(args.log_file)

src/main/scala/top/Top.scala

@@ -20,7 +20,7 @@ package top
 import chisel3._
 import chisel3.util._
 import chisel3.experimental.dataview._
-import difftest.DifftestModule
+import difftest.{DifftestModule, DifftestTopIO, HasDiffTestInterfaces}
 import xiangshan._
 import utils._
 import utility._
@@ -44,10 +44,9 @@ import freechips.rocketchip.amba.axi4._
 import freechips.rocketchip.jtag.JTAGIO
 import chisel3.experimental.annotate
 import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
-import scala.collection.mutable.{Map}
 
-import difftest.common.DifftestWiring
-import difftest.util.Profile
+import scala.collection.mutable.Map
+import difftest.gateway.Gateway
 
 abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
   with HasSoCParameter
@@ -476,11 +475,24 @@ class XSTop()(implicit p: Parameters) extends BaseXSSoc()
 class XSTileDiffTop(implicit p: Parameters) extends XSTop {
   //TODO: need to keep the same module name as XSNoCDiffTop
   override lazy val desiredName: String = "XSTop"
-  class XSTileDiffTopImp(wrapper: XSTop) extends XSTopImp(wrapper) {
-    DifftestWiring.createAndConnectExtraIOs()
-    Profile.generateJson("XiangShan")
-  }
 
+  class XSTileDiffTopImp(wrapper: XSTop) extends XSTopImp(wrapper) with HasDiffTestInterfaces {
+    override def cpuName: Option[String] = Some("XiangShan")
+    override protected def implicitClock: Clock = io.clock
+    override protected def implicitReset: Reset = io.reset
+    override def connectTopIOsWithName(difftest: DifftestTopIO): Seq[(Data, String)] = {
+      val otherIOs = Seq(wrapper.nmi.getWrappedValue) ++
+        dma.toSeq ++
+        Seq(
+          memory,
+          peripheral,
+        )
+      otherIOs.map(d => (d, d.instanceName)) ++
+        io.elements.toSeq.collect { case (name, elem)
+          if !Seq("clock", "reset").contains(name) => (elem, "io_" + name)
+        }
+    }
+  }
   override lazy val module = new XSTileDiffTopImp(this)
 }
 
@@ -500,8 +512,13 @@ object TopMain extends App {
     Generator.execute(firrtlOpts, soc.module, firtoolOpts)
   } else if (config(SoCParamsKey).UseXSTileDiffTop) {
     val soc = DisableMonitors(p => LazyModule(new XSTileDiffTop()(p)))(config)
-    Generator.execute(firrtlOpts, soc.module, firtoolOpts)
+    Generator.execute(firrtlOpts, DifftestModule.top(soc.module), firtoolOpts)
   } else {
+    if (enableDifftest) {
+      // TODO: Temporarily force XSTop to use internal DPI-C; will later split Top and Difftest like DiffTop
+      Gateway.setConfig("U")
+    }
+
     val soc = if (config(SoCParamsKey).UseXSNoCTop)
       DisableMonitors(p => LazyModule(new XSNoCTop()(p)))(config)
     else

src/main/scala/xiangshan/backend/Backend.scala

@@ -491,10 +491,6 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame
   dataPath.io.fromVfWb := wbDataPath.io.toVfPreg
   dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg
   dataPath.io.fromVlWb := wbDataPath.io.toVlPreg
-  dataPath.io.diffIntRat.foreach(_ := ctrlBlock.io.diff_int_rat.get)
-  dataPath.io.diffFpRat .foreach(_ := ctrlBlock.io.diff_fp_rat.get)
-  dataPath.io.diffVecRat.foreach(_ := ctrlBlock.io.diff_vec_rat.get)
-  dataPath.io.diffV0Rat .foreach(_ := ctrlBlock.io.diff_v0_rat.get)
   dataPath.io.diffVlRat .foreach(_ := ctrlBlock.io.diff_vl_rat.get)
   dataPath.io.fromBypassNetwork := bypassNetwork.io.toDataPath
   dataPath.io.fromVecExcpMod.r := vecExcpMod.o.toVPRF.r

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -629,6 +629,7 @@ class CtrlBlockImp(
   memCtrl.io.mdpFlodPcVec := mdpFlodPcVec
   memCtrl.io.dispatchLFSTio <> dispatch.io.lfst
 
+  rat.io.hartId := io.fromTop.hartId
   rat.io.redirect := s1_s3_redirect.valid
   rat.io.rabCommits := rob.io.rabCommits
   rat.io.diffCommits.foreach(_ := rob.io.diffCommits.get)
@@ -776,10 +777,6 @@ class CtrlBlockImp(
   // rob to mem block
   io.robio.lsq <> rob.io.lsq
 
-  io.diff_int_rat.foreach(_ := rat.io.diff_int_rat.get)
-  io.diff_fp_rat .foreach(_ := rat.io.diff_fp_rat.get)
-  io.diff_vec_rat.foreach(_ := rat.io.diff_vec_rat.get)
-  io.diff_v0_rat .foreach(_ := rat.io.diff_v0_rat.get)
   io.diff_vl_rat .foreach(_ := rat.io.diff_vl_rat.get)
 
   rob.io.debug_ls := io.robio.debug_ls
@@ -975,10 +972,6 @@ class CtrlBlockIO()(implicit p: Parameters, params: BackendParams) extends XSBun
       val lsdqFull  = Bool()
     }
   })
-  val diff_int_rat = if (params.basicDebugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None
-  val diff_fp_rat  = if (params.basicDebugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None
-  val diff_vec_rat = if (params.basicDebugEn) Some(Vec(31, Output(UInt(PhyRegIdxWidth.W)))) else None
-  val diff_v0_rat  = if (params.basicDebugEn) Some(Vec(1, Output(UInt(PhyRegIdxWidth.W)))) else None
   val diff_vl_rat  = if (params.basicDebugEn) Some(Vec(1, Output(UInt(PhyRegIdxWidth.W)))) else None
 
   val sqCanAccept = Input(Bool())

src/main/scala/xiangshan/backend/datapath/DataPath.scala

@@ -3,7 +3,7 @@ package xiangshan.backend.datapath
 import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
-import difftest.{DiffArchFpRegState, DiffArchIntRegState, DiffArchVecRegState, DifftestModule}
+import difftest._
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import utility._
 import utils.SeqUtils._
@@ -267,38 +267,29 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
   io.fromPcTargetMem.fromDataPathFtqPtr := pcReadFtqPtr
   io.fromPcTargetMem.fromDataPathFtqOffset := pcReadFtqOffset
 
-  private val intDiffRead: Option[(Vec[UInt], Vec[UInt])] =
-    OptionWrapper(backendParams.basicDebugEn, (Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W)))))
-  private val fpDiffRead: Option[(Vec[UInt], Vec[UInt])] =
-    OptionWrapper(backendParams.basicDebugEn, (Wire(Vec(32, UInt(fpSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W)))))
-  private val vfDiffRead: Option[(Vec[UInt], Vec[UInt])] =
-    OptionWrapper(backendParams.basicDebugEn, (Wire(Vec(31, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(31, UInt(VLEN.W)))))
-  private val v0DiffRead: Option[(Vec[UInt], Vec[UInt])] =
-    OptionWrapper(backendParams.basicDebugEn, (Wire(Vec(1, UInt(log2Up(V0PhyRegs).W))), Wire(Vec(1, UInt(V0Data().dataWidth.W)))))
+  private val intDiffReadData: Option[Vec[UInt]] =
+    OptionWrapper(backendParams.basicDebugEn, Wire(Vec(intSchdParams.numPregs, UInt(XLEN.W))))
+  private val fpDiffReadData: Option[Vec[UInt]] =
+    OptionWrapper(backendParams.basicDebugEn, Wire(Vec(fpSchdParams.numPregs, UInt(XLEN.W))))
+  private val vfDiffReadData: Option[Vec[UInt]] =
+    OptionWrapper(backendParams.basicDebugEn, Wire(Vec(vfSchdParams.numPregs, UInt(VLEN.W))))
+  private val v0DiffReadData: Option[Vec[UInt]] =
+    OptionWrapper(backendParams.basicDebugEn, Wire(Vec(V0PhyRegs, UInt(V0Data().dataWidth.W))))
   private val vlDiffRead: Option[(Vec[UInt], Vec[UInt])] =
     OptionWrapper(backendParams.basicDebugEn, (Wire(Vec(1, UInt(log2Up(VlPhyRegs).W))), Wire(Vec(1, UInt(VlData().dataWidth.W)))))
 
-  private val fpDiffReadData: Option[Vec[UInt]] =
-    OptionWrapper(backendParams.basicDebugEn, Wire(Vec(32, UInt(XLEN.W))))
+  private val vecDiffNumPregs = 2 * (V0PhyRegs + vfSchdParams.numPregs)
   private val vecDiffReadData: Option[Vec[UInt]] =
-    OptionWrapper(backendParams.basicDebugEn, Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0))
+    OptionWrapper(backendParams.basicDebugEn, Wire(Vec(vecDiffNumPregs, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0))
   private val vlDiffReadData: Option[UInt] =
     OptionWrapper(backendParams.basicDebugEn, Wire(UInt(VlData().dataWidth.W)))
 
-
-  fpDiffReadData.foreach(_ := fpDiffRead
-    .get._2
-    .slice(0, 32)
-    .map(_(63, 0))
-  ) // fp only used [63, 0]
   vecDiffReadData.foreach(_ := 
-    v0DiffRead
-    .get._2
-    .slice(0, 1)
+    v0DiffReadData
+    .get
     .map(x => Seq(x(63, 0), x(127, 64))).flatten ++ 
-    vfDiffRead
-    .get._2
-    .slice(0, 31)
+    vfDiffReadData
+    .get
     .map(x => Seq(x(63, 0), x(127, 64))).flatten
   )
   vlDiffReadData.foreach(_ := vlDiffRead
@@ -309,22 +300,37 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
 
   IntRegFileSplit("IntRegFile", intSchdParams.numPregs, splitNum = 4, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata,
     bankNum = 1,
-    debugReadAddr = intDiffRead.map(_._1),
-    debugReadData = intDiffRead.map(_._2)
+    debugAllRData = intDiffReadData
   )
+  if (env.AlwaysBasicDiff || env.EnableDifftest) {
+    // Delay of PhyRegFile should be same as RenameTable
+    val difftest = DifftestModule(new DiffPhyIntRegState(intSchdParams.numPregs), delay = 2)
+    difftest.coreid := io.hartId
+    difftest.value := intDiffReadData.get
+  }
+
   FpRegFileSplit("FpRegFile", fpSchdParams.numPregs, splitNum = 4, fpRfRaddr, fpRfRdata, fpRfWen, fpRfWaddr, fpRfWdata,
     bankNum = 1,
-    debugReadAddr = fpDiffRead.map(_._1),
-    debugReadData = fpDiffRead.map(_._2)
+    debugAllRData = fpDiffReadData
   )
+  if (env.AlwaysBasicDiff || env.EnableDifftest) {
+    val difftest = DifftestModule(new DiffPhyFpRegState(fpSchdParams.numPregs), delay = 2)
+    difftest.coreid := io.hartId
+    difftest.value := fpDiffReadData.get
+  }
+
   VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata,
-    debugReadAddr = vfDiffRead.map(_._1),
-    debugReadData = vfDiffRead.map(_._2)
+    debugAllRData = vfDiffReadData
   )
   VfRegFile("V0RegFile", V0PhyRegs, v0RfSplitNum, v0RfRaddr, v0RfRdata, v0RfWen, v0RfWaddr, v0RfWdata,
-    debugReadAddr = v0DiffRead.map(_._1),
-    debugReadData = v0DiffRead.map(_._2)
+    debugAllRData = v0DiffReadData
   )
+  if (env.AlwaysBasicDiff || env.EnableDifftest) {
+    val difftest = DifftestModule(new DiffPhyVecRegState(vecDiffNumPregs), delay = 2)
+    difftest.coreid := io.hartId
+    difftest.value := vecDiffReadData.get
+  }
+
   FpRegFile("VlRegFile", VlPhyRegs, vlRfRaddr, vlRfRdata, vlRfWen, vlRfWaddr, vlRfWdata,
     bankNum = 1,
     isVlRegfile = true,
@@ -424,30 +430,15 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
       vlRfRaddr(portIdx) := 0.U
   }
 
-
-  intDiffRead.foreach { case (addr, _) =>
-    addr := io.diffIntRat.get
-  }
-
-  fpDiffRead.foreach { case (addr, _) =>
-    addr := io.diffFpRat.get
-  }
-
-  vfDiffRead.foreach { case (addr, _) =>
-    addr := io.diffVecRat.get
-  }
-  v0DiffRead.foreach { case (addr, _) =>
-    addr := io.diffV0Rat.get
-  }
   vlDiffRead.foreach { case (addr, _) =>
     addr := io.diffVlRat.get
   }
 
   println(s"[DataPath] " +
-    s"has intDiffRead: ${intDiffRead.nonEmpty}, " +
-    s"has fpDiffRead: ${fpDiffRead.nonEmpty}, " +
-    s"has vecDiffRead: ${vfDiffRead.nonEmpty}, " +
-    s"has v0DiffRead: ${v0DiffRead.nonEmpty}, " +
+    s"has intDiffRead: ${intDiffReadData.nonEmpty}, " +
+    s"has fpDiffRead: ${fpDiffReadData.nonEmpty}, " +
+    s"has vecDiffRead: ${vfDiffReadData.nonEmpty}, " +
+    s"has v0DiffRead: ${v0DiffReadData.nonEmpty}, " +
     s"has vlDiffRead: ${vlDiffRead.nonEmpty}")
 
   // regcache
@@ -725,21 +716,6 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
     }
   }
 
-  if (env.AlwaysBasicDiff || env.EnableDifftest) {
-    val delayedCnt = 2
-    val difftestArchIntRegState = DifftestModule(new DiffArchIntRegState, delay = delayedCnt)
-    difftestArchIntRegState.coreid := io.hartId
-    difftestArchIntRegState.value := intDiffRead.get._2
-
-    val difftestArchFpRegState = DifftestModule(new DiffArchFpRegState, delay = delayedCnt)
-    difftestArchFpRegState.coreid := io.hartId
-    difftestArchFpRegState.value := fpDiffReadData.get
-
-    val difftestArchVecRegState = DifftestModule(new DiffArchVecRegState, delay = delayedCnt)
-    difftestArchVecRegState.coreid := io.hartId
-    difftestArchVecRegState.value := vecDiffReadData.get
-  }
-
   val int_regcache_size = 48
   val int_regcache_tag = RegInit(VecInit(Seq.fill(int_regcache_size)(0.U(intSchdParams.pregIdxWidth.W))))
   val int_regcache_enqPtr = RegInit(0.U(log2Up(int_regcache_size).W))
@@ -966,10 +942,6 @@ class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBund
     Output(UInt(RegCacheIdxWidth.W))
   )
 
-  val diffIntRat = if (params.basicDebugEn) Some(Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W)))) else None
-  val diffFpRat  = if (params.basicDebugEn) Some(Input(Vec(32, UInt(fpSchdParams.pregIdxWidth.W)))) else None
-  val diffVecRat = if (params.basicDebugEn) Some(Input(Vec(31, UInt(vfSchdParams.pregIdxWidth.W)))) else None
-  val diffV0Rat  = if (params.basicDebugEn) Some(Input(Vec(1, UInt(log2Up(V0PhyRegs).W)))) else None
   val diffVlRat  = if (params.basicDebugEn) Some(Input(Vec(1, UInt(log2Up(VlPhyRegs).W)))) else None
   val diffVl     = if (params.basicDebugEn) Some(Output(UInt(VlData().dataWidth.W))) else None