submodule(difftest): refactor DiffTop, PhyReg and Refill #5188
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Latest difftest introduces following notable change: 1. CPU as submodule of Difftest Difftest now allows instantiating the CPU as a submodule and exposing additional IOs. LazyModules must explicitly provide clock and reset signals. (PRs: difftest#713, difftest#757, difftest#758) 2. Replace ArchReg + WriteBack with PhyReg + RenameTable The old embedded-into-CPU Difftest logic is removed. The new PhyReg + RenameTable interface eliminates additional phy-to-arch logic and multi- read-port overhead inside the CPU and removes interface of ArchReg/WriteBack. (PRs: difftest#714, difftest#754) 3. RefillEvent interface modification Refill checking now support masked refill-check to support low-power read. (PRs: difftest#719, difftest#723) 4. PGO_BOLT option for emu compilation A new PGO_BOLT mode is provided to accelerate EMU compilation under profile-guided optimization. (PR: difftest#756, difftest#761)
This change moves XSDiffTop instantiation into the Difftest for fpgaDiff. DiffTop will generated with a SimTop wrapper, where DiffTest outputs, together with XSTop's IO ports, AXI4 buses of memory/peripheral/DMA will be exposed for external connection. Temporarily, we still expose XSNoCDiffTop with appended Difftest IOs, and generate XSTop and XSNoCTop with internal Difftest DPI-C, so as to avoid extra TopIOs and mixed generated files. We will try to refactor them like DiffTop later.(i.e. generate with a seperated Difftest)
This change refactors Difftest interfaces, replacing the previous ArchReg and WriteBack with PhyRegState and ArchRenameTable. By default, Difftest still extracts PhyReg and RenameTable into ArchReg on the hardware side, so that the extra multi-read area is accounted for within Difftest. When acceleration is enabled, this extraction is deferred to the software side, eliminating the extra hardware area overhead. Since 128-bit ArchVecReg are now treated as two 64-bit registers in Difftest, we add corresponding register splitting in XiangShan. The address indexs (InstrCommit.otherwpdest and RenameTable) are also converted from `index` to `2*index` and `2*index + 1` for reg splitting. Note XiangShan separates V0 and Vf register files. When mering the two regfiles and renameTable for Difftest, the indexs of Vf must add offset of V0RegSize to ensure correct indexing.
After #3051, we have supported low-power read (read only 5 out of 8 8B-banks) in ICacheDataArray, and in V3, it was further modified to dynamically compute the mask based on the taken branch location. Though, previous DiffRefillEvent does not support masked comparison, instead it checks entire 512bit, so it will fail if we enable checks on cacheid >=3 (OpenXiangShan/difftest#712). As we're refactoring ICache recently, we need this check to ensure the refactored code is working properly. This commit removes unused idtfr and introduces masked refill-check for Difftest, where each mask bit controls comparison of 8B data. However, as the newly added masked Refill fails CI, we disable it for now, and wait for later fixup. Co-authored-by: ngc7331 <[email protected]>
This change unifies the args handling for PLDM and FPGA_DIFF into a shared DEBUG_ARGS options, with PLDM=1 or FPGA=1 used to distinguish between the two environments. For PLDM, we continue to enable the full Difftest by default as it used to be. For FPGA, we set it default to BASIC_DIFF and remove additional debug printing to reduce overhead. Any extra options can be supplied via DEBUG_ARGS as needed. Example usage: PLDM=1 DEBUG_ARGS="--difftest-config ZESN --perf-level CRITICAL" FPGA=1 DEBUG_ARGS="--difftest-config ESBIFDU --difftest-exclude Vec"
This PR updates the xspdb to adapt to the API changes. --------- Co-authored-by: Zhicheng Yao <[email protected]>
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submodule(difftest): refactor DiffTop, PhyReg, Refill, PGO_BOLT
Latest difftest introduces following notable change:
CPU as submodule of Difftest
Difftest now allows instantiating the CPU as a submodule and exposing
additional IOs. LazyModules must explicitly provide clock and reset
signals.
(PRs: feat(top): allow extra CPU IO with connectTopIOs difftest#713, feat(top): support extra Clock and Reset for RawModule difftest#757, feat(top): support createTopIOs with explicit name difftest#758)
Replace ArchReg + WriteBack with PhyReg + RenameTable
The old embedded-into-CPU Difftest logic is removed. The new PhyReg +
RenameTable interface eliminates additional phy-to-arch logic and multi-
read-port overhead inside the CPU and removes interface of ArchReg/WriteBack.
(PRs: feat(difftest): support DiffPhyRegState and DiffArchRenameTable difftest#714, refactor(difftest): remove DiffWriteback and privatize DiffArchReg difftest#754)
RefillEvent interface modification
Refill checking now support masked refill-check to support low-power
read.
(PRs: fix(difftest): remove unused idtfr from RefillEvent difftest#719, feat(refill-check): add mask to refill check difftest#723)
PGO_BOLT option for emu compilation
A new PGO_BOLT mode is provided to accelerate EMU compilation under
profile-guided optimization.
(PR: feat(verilator,gsim): add PGO_BOLT option difftest#756)
feat(top): adapt difftest interfaces for FPGA difftest
This change moves XSDiffTop instantiation into the Difftest for fpgaDiff.
DiffTop will generated with a SimTop wrapper, where DiffTest outputs,
together with XSTop's IO ports, AXI4 buses of memory/peripheral/DMA will
be exposed for external connection.
Temporarily, we still expose XSNoCDiffTop with appended Difftest IOs, and
generate XSTop and XSNoCTop with internal Difftest DPI-C, so as to avoid
extra TopIOs and mixed generated files. We will try to refactor them like
DiffTop later.(i.e. generate with a seperated Difftest)
feat(difftest): replace ArchReg and Writeback with PhyRegState
This change refactors Difftest interfaces, replacing the previous
ArchReg and WriteBack with PhyRegState and ArchRenameTable.
By default, Difftest still extracts PhyReg and RenameTable into
ArchReg on the hardware side, so that the extra multi-read area
is accounted for within Difftest.
When acceleration is enabled, this extraction is deferred to the
software side, eliminating the extra hardware area overhead.
Since 128-bit ArchVecReg are now treated as two 64-bit registers
in Difftest, we add corresponding register splitting in XiangShan.
The address indexs (InstrCommit.otherwpdest and RenameTable) are
also converted from
indexto2*indexand2*index + 1for regsplitting.
Note XiangShan separates V0 and Vf register files. When mering the
two regfiles and renameTable for Difftest, the indexs of Vf must
add offset of V0RegSize to ensure correct indexing.
fix(difftest): add masked RefillEvent, disable for now
After Frontend new ICache #3051, we have supported low-power read (read only 5 out of 8
8B-banks) in ICacheDataArray, and in V3, it was further modified to
dynamically compute the mask based on the taken branch location.
Though, previous DiffRefillEvent does not support masked comparison,
instead it checks entire 512bit, so it will fail if we enable checks on
cacheid >=3 (fix(difftest): only check existed refill events difftest#712). As we're refactoring ICache
recently, we need this check to ensure the refactored code is working
properly.
This commit removes unused idtfr and introduces masked refill-check
for Difftest, where each mask bit controls comparison of 8B data.
However, as the newly added masked Refill fails CI, we disable it for
now, and wait for later fixup.
Co-authored-by: ngc7331 [email protected]
fix(Makefile): unify PLDM and FPGA args under DEBUG_ARGS
This change unifies the args handling for PLDM and FPGA_DIFF into a shared
DEBUG_ARGS options, with PLDM=1 or FPGA=1 used to distinguish between the
two environments.
For PLDM, we continue to enable the full Difftest by default as it used to
be. For FPGA, we set it default to BASIC_DIFF and remove additional debug
printing to reduce overhead. Any extra options can be supplied via
DEBUG_ARGS as needed.
Example usage:
PLDM=1 DEBUG_ARGS="--difftest-config ZESN --perf-level CRITICAL"
FPGA=1 DEBUG_ARGS="--difftest-config ESBIFDU --difftest-exclude Vec"
fix(pdb): resolve API incompatibility with difftest update
This PR updates the xspdb to adapt to the API changes.
Co-authored-by: SFangYy [email protected]
Co-authored-by: Zhicheng Yao [email protected]