SJTU-YONGFU-RESEARCH-GRP
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Repositories
- core-cc Public
A comprehensive framework for benchmarking, analyzing, and comparing different Error Correction Code (ECC) implementations with support for hardware verification, detailed performance analysis, and parallel processing capabilities.
SJTU-YONGFU-RESEARCH-GRP/core-cc’s past year of commit activity - core-ddr2 Public
This repository contains a JEDEC-style DDR2 SDRAM controller targeting the memory devices. The controller exposes a simple FIFO-like front-end interface and maps host commands into DDR2 transactions, including full power-up initialization, periodic refresh, scalar and block reads/writes, and DQS-based data capture.
SJTU-YONGFU-RESEARCH-GRP/core-ddr2’s past year of commit activity - ACLD-Asynchronous-Circuit-Logic-Dataset Public
A comprehensive collection of asynchronous circuit logic designs, featuring 4 pipeline structures and 26 asynchronous design templates based on 6 data channel configurations. The dataset contains 120 asynchronous circuit logic designs, serving as a valuable resource for simulating and evaluating diverse asynchronous design methods.
SJTU-YONGFU-RESEARCH-GRP/ACLD-Asynchronous-Circuit-Logic-Dataset’s past year of commit activity - verilog_spice_conversion Public
This tool converts Verilog RTL designs to SPICE netlists using Yosys for synthesis. It supports hierarchical, flattened, and fully-flattened (with embedded cell models) output formats.
SJTU-YONGFU-RESEARCH-GRP/verilog_spice_conversion’s past year of commit activity - spice_netlist_parser Public
A robust, AST-based parser for SPICE netlist files with comprehensive analysis and validation capabilities.
SJTU-YONGFU-RESEARCH-GRP/spice_netlist_parser’s past year of commit activity - awesome-systemverilog-uvm Public
A comprehensive one-stop hub for learning Universal Verification Methodology (UVM), accessing powerful verification tools, and exploring reference designs.
SJTU-YONGFU-RESEARCH-GRP/awesome-systemverilog-uvm’s past year of commit activity - spice_model_benchmark Public
This project provides a comprehensive benchmarking system for SPICE models, allowing for the automated verification and validation of semiconductor device models with a focus on MOSFETs.
SJTU-YONGFU-RESEARCH-GRP/spice_model_benchmark’s past year of commit activity - spice_netlist_generator Public
A Python CLI tool for generating random SPICE (Simulation Program with Integrated Circuits Emphasis) netlists with configurable device types, connectivity guarantees, and ngspice simulation integration.
SJTU-YONGFU-RESEARCH-GRP/spice_netlist_generator’s past year of commit activity - SPRSound Public
This repository contains the released respiratory sound database for IEEE BioCAS Respiratory Sound Track Challenges.
SJTU-YONGFU-RESEARCH-GRP/SPRSound’s past year of commit activity
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