Awesome SystemVerilog UVM

A comprehensive one-stop hub for learning Universal Verification Methodology (UVM), accessing powerful verification tools, and exploring reference designs.

📚 Overview

This repository serves as a centralized resource for SystemVerilog UVM verification engineers, providing:

• 📖 Learning Materials: Curated tutorials, primers, and reference guides
• 🛠️ Development Tools: Essential tools for UVM verification workflow
• 🎯 Reference Designs: Production-ready verification components and examples

🚀 Quick Start

Prerequisites

• Python 3.7+
• SystemVerilog simulator (QuestaSim, VCS, Xcelium, or similar)
• Git for submodule management

Installation

# Clone the repository with submodules
git clone --recursive https://github.com/SJTU-YONGFU-RESEARCH-GRP/awesome-systemverilog-uvm.git
cd awesome-systemverilog-uvm

# Initialize submodules if not done during clone
git submodule update --init --recursive

📖 Learning Resources

Dive into UVM with our curated collection of learning materials:

📚 Core UVM Learning

• UVM Reference - Official Accellera UVM reference implementation and documentation
• UVM Primer - Ray Salemi's comprehensive UVM tutorial series
• Learn UVM PyUVM - Integrated learning materials for both SystemVerilog UVM and PyUVM

🐍 Python for Verification

• Python4RTLVerification - Python techniques for RTL verification workflows

🔧 FPGA Simulation

• FPGASimulation - FPGA-specific simulation methodologies and best practices

🛠️ Development Tools

Accelerate your verification workflow with these powerful tools:

🔄 Language Translation

• PyUVM SV-UVM Translator - Seamless translation between PyUVM and SystemVerilog UVM components

📊 Code Analysis

• PyUVM Analyzer - Static analysis and optimization tools for PyUVM codebases
• PySystemVerilog Analyzer - Advanced analysis tools for SystemVerilog verification code

🐍 Python-Based Verification

• Cocotb - Python-based hardware verification framework with coroutine support

🎯 Reference Designs

AXI Protocol Verification

UVM AXI - Complete AXI protocol verification environment featuring:

• AXI BFM with comprehensive protocol checking
• Virtual Master/Slave components for flexible test scenarios
• Protocol Checker supporting:
  • Read/Write phase validation
  • ID tag mapping verification
  • Transfer integrity checks
• TLM Analysis Ports for third-party integration
• DPI/PLI Interfaces for system-level verification
• Ready-to-run Examples with Python automation scripts

Quick AXI Demo

cd designs/uvm_axi
python run.py  # Runs the virtual master to DUT slave example

📋 Directory Structure

awesome-systemverilog-uvm/
├── learnings/              # Educational resources and tutorials
│   ├── UVMReference/       # Official UVM reference materials
│   ├── uvmprimer/          # UVM primer tutorials
│   ├── learn_uvm_pyuvm/    # Integrated UVM/PyUVM learning
│   ├── Python4RTLVerification/  # Python verification techniques
│   └── fpgasimulation/     # FPGA simulation resources
├── tools/                  # Development and analysis tools
│   ├── cocotb/            # Python verification framework
│   ├── pyuvm_svuvm_translator/  # Language translation tools
│   ├── pyuvm_analyzer/     # PyUVM analysis utilities
│   └── pysystemverilog_analyzer/  # SystemVerilog analysis tools
└── designs/               # Reference verification environments
    └── uvm_axi/           # AXI protocol verification suite

🎓 Learning Path

📖 Learning Materials

1. UVM Primer - Foundational concepts and comprehensive tutorial series
2. UVM Reference - Official Accellera UVM implementation and documentation
3. Learn UVM PyUVM - Integrated learning for both SystemVerilog UVM and PyUVM
4. Python4RTLVerification - Python techniques for RTL verification workflows
5. FPGA Simulation - FPGA-specific simulation methodologies and best practices

🛠️ Development Tools

1. Cocotb - Python-based hardware verification framework with coroutine support
2. PyUVM Analyzer - Static analysis and optimization tools for PyUVM codebases
3. PySystemVerilog Analyzer - Advanced analysis tools for SystemVerilog verification code
4. PyUVM SV-UVM Translator - Seamless translation between PyUVM and SystemVerilog UVM components

🎯 Reference Designs

1. UVM AXI - Complete AXI protocol verification environment with:
   • AXI BFM with comprehensive protocol checking
   • Virtual Master/Slave components
   • Protocol validation and analysis ports
   • Ready-to-run examples with Python automation

🤝 Contributing

We welcome contributions to enhance this verification ecosystem!

Adding New Resources

1. Fork the repository
2. Add your learning material, tool, or design as a submodule
3. Update this README with appropriate documentation
4. Submit a pull request

Guidelines

• Ensure all submodules have proper licensing
• Include comprehensive documentation
• Add practical examples where applicable
• Test integration with existing tools

📄 License

This repository is licensed under Creative Commons Attribution 4.0 International (CC BY 4.0).

You are free to:

• Share — copy and redistribute the material in any medium or format
• Adapt — remix, transform, and build upon the material for any purpose, even commercially

Under the following terms:

• Attribution — You must give appropriate credit, provide a link to the license, and indicate if changes were made

This repository contains multiple submodules with their own licenses. Please refer to each submodule's license file for specific terms regarding individual components.

🙏 Acknowledgments

• Accellera for the UVM standard
• Ray Salemi for educational content and tutorials
• Cocotb Community for Python-based verification framework
• SJTU-YONGFU-RESEARCH-GRP for specialized UVM tools
• Verification Excellence for UVM reference materials

📞 Support

• 📧 Issues: GitHub Issues
• 📖 Documentation: Check individual submodule READMEs for detailed usage
• 💬 Discussions: GitHub Discussions

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Empowering the verification community with comprehensive UVM resources and tools.