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1. rtl-ahb-to-apb-bridge rtl-ahb-to-apb-bridge Public

   🚀 Synthesizable Verilog RTL implementation of an AMBA AHB-to-APB protocol bridge using a finite state machine (FSM).Designed for integration in SoC and IP subsystems that interface high-performance…

   Verilog 1

2. rtl-fifo-designs rtl-fifo-designs Public

   🚀 RTL design of synchronous and dual-clock asynchronous FIFO buffers in Verilog, featuring flow control, pointer logic, and waveform-based validation.

   Verilog

3. electronic-voting-machine-verilog electronic-voting-machine-verilog Public

   🚀 RTL design and testbench implementation of a Digital Electronic Voting Machine (EVM) using Verilog HDL. The EVM is modeled with a modular, FSM-based architecture suitable for FPGA or ASIC prototy…

   Verilog

4. rtl-protocol-designs rtl-protocol-designs Public template

   ⚙️ A curated RTL library of digital communication protocols — including AMBA(AHB/APB/AXI), UART, SPI, I2C, and FIFO-based buffering — designed in Verilog for synthesis, simulation, and SoC intercon…

   Verilog 2

5. machine-learning-lab-EEEG513-bits machine-learning-lab-EEEG513-bits Public

   Lab assignments for Machine Learning for Electronics Engineers (EEE G513) - Python implementations.

   Jupyter Notebook