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Add initital H extension support (Without Full AIA support)#120

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inochisa wants to merge 80 commits intoSpinalHDL:devfrom
project-inochi:ext-h
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Add initital H extension support (Without Full AIA support)#120
inochisa wants to merge 80 commits intoSpinalHDL:devfrom
project-inochi:ext-h

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@inochisa inochisa commented Feb 21, 2026 •
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Add basic support for H extension.

This PR includes the following part:

  1. introduce a new method to remap the VS-stage S-mode CSR access to VS-stage, also add necessary api for HS-mode permission check
  2. Add basic hypervisor CSR support.
  3. Adjust TrapPlugin to support VS-stage interrupt.
  4. Adapt the sstc/smcsrind/sscsrind to hypervisor extension
  5. G-stage MMU support

This PR does not include:

  1. G-stage MMU support.
  2. Full AIA extension support for H extension.

Edit:
20260316: Add G-stage MMU support

@inochisa inochisa force-pushed the ext-h branch 2 times, most recently from e377e14 to 6fba459 Compare March 2, 2026 04:47
@looongbin looongbin force-pushed the ext-h branch 2 times, most recently from d980e58 to 831055e Compare March 4, 2026 04:02
@looongbin looongbin force-pushed the ext-h branch 2 times, most recently from a51f9e8 to acf2678 Compare March 5, 2026 07:17
@inochisa inochisa marked this pull request as draft March 9, 2026 02:57
inochisa and others added 19 commits March 16, 2026 15:39
@inochisa
Add RVH instruction definition
ef41c55 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Add AIA CSR definition for hypervisor mode
ff4d909 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Fix wrong hypervisor CSR id
96095a5 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Add remapWhen() to allow to remap CSR address to another one
9a3b68c 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@looongbin @inochisa
Check CSR permission from UOP to avoid permission change when remappi…
e87ede0 
…ng id

Signed-off-by: Longbin Li <looong.bin@gmail.com>
@inochisa
Add initial machine mode logic for hypervisor
2cd5162 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Add initial hypervisor mode logic
2caca16 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Add initial hypervisor interrupt routing logic
075f61b 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Add RVH CPU parameter trampoline
b711631 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Make Some supervisor HS-mode only
829888e 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Add initial trap logic for VS mode
93f8b96 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Add counter performance support for hypervisor
3c138a7 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Add counter enable and time delta logic support
da512d3 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Add hypervisor mode SSTC support
486d288 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@looongbin @inochisa
replace privilegeMux's logic by hashmap
001a1ff 
Signed-off-by: Longbin Li <looong.bin@gmail.com>
@looongbin @inochisa
add H mode support of interrupt and exception
97b5e1c 
Signed-off-by: Longbin Li <looong.bin@gmail.com>
@inochisa
Replace hardwire value with pre-defined value
7ff17c5 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Add hypervisor check for VTVM/VTSR/VTW bit
c15ff42 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@looongbin @inochisa
Write 0 to h.tval/m.tval2 and tinst when trap to 'M/S'
7726efa 
Signed-off-by: Longbin Li <looong.bin@gmail.com>
inochisa and others added 27 commits March 16, 2026 15:39
@inochisa
Write pseudoinstruction value to htinst/mtinst when triggering guest …
9db5846 
…page fault.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@sycamoremoon @inochisa
Add Guest Translation indicator for TLB
0a39b4f
@sycamoremoon @inochisa
Use vsstatus/vsatp for guest translations
b9c2035 
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
@sycamoremoon @inochisa
Use nominal privilege when HSV/HLV
9c112d5 
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
@inochisa
Add bypass mode when hgatp is bare
4f1a591 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Report both page fault and access fault in the DBus request translation
1ebe7d7 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Report access fault in the G-stage refill
2662c70 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Always record GPA for a two stage translation
5fc7e5b 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Add permission check for PTE refill in ShadowMmuPlugin
5f9fb6a 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Add tval2 to TrapPort
0f025d2 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
fix FPU in hypervisor
d11d5db 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@sycamoremoon @inochisa
Change Fetch L1 ATS pipeline style
3431201 
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
@inochisa
[tmp] Make L1 LSU 4 stage
5d5c198 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@sycamoremoon @inochisa
[tmp] Make Fetch L1 4-stages
f74f40a 
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
@sycamoremoon @inochisa
[tmp] Make Fetch Cacheless 4-stages
9c6ab5a 
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
@sycamoremoon @inochisa
[tmp] Make cacheless LSU 4-stages
39b608f 
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
@inochisa
[tmp] Add initial L1 LSU two-stage translation support
3425ccc 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
[tmp] Add initial cacheless LSU two-stage translation support
d5048a2 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@sycamoremoon @inochisa
[tmp] Add initial Fetch L1 two-stage translation support
bb0b4b0 
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
@sycamoremoon @inochisa
[tmp] Add initial Fetch Cacheless two-stage translation support
db0a3d0 
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
@inochisa
Check address sign extension based on actual LSU state for LsuPlugin
1a483d8 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Handle execute permssion requested by HLVX.WU and HLVX.HU
68a6758 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Allow to set fail symbol for TestBench
b498335 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa
Update Fetch L1 plugin hit logic
d8715ad 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@looongbin @inochisa
[fix] prevent delegating to HU/VU mode
99a62ef 
Signed-off-by: Longbin Li <looong.bin@gmail.com>
@looongbin @inochisa
[tmp] add senvcfg
ab0db2d 
Signed-off-by: Longbin Li <looong.bin@gmail.com>
@inochisa
Report right fault address for shadow MMU
3aa79a7 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
@inochisa inochisa changed the title Add initital H extension support (Without G-stage MMU/Full AIA support) Add initital H extension support (Without Full AIA support) Mar 16, 2026
@inochisa
[fix] fix htval address
42873b3 
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
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3 participants

@inochisa @looongbin @sycamoremoon